[SCSI] pm80xx: Device id changes to support series 8 controllers.
Updated pci id table with device, vendor, subdevice and subvendor ids for 8074, 8076, 8077 SAS/SATA 12G controllers. Added 12G related macros. Signed-off-by: Anandkumar.Santhanam@pmcs.com Reviewed-by: Jack Wang <jinpu.wang@profitbricks.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>hifive-unleashed-5.1
Anand Kumar Santhanam
James Bottomley
parent
c712495e68
commit
a9a923e55e
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@ -46,7 +46,10 @@ enum chip_flavors {
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chip_8008,
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chip_8009,
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chip_8018,
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chip_8019
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chip_8019,
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chip_8074,
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chip_8076,
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chip_8077
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};
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enum phy_speed {
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@ -54,6 +54,9 @@ static const struct pm8001_chip_info pm8001_chips[] = {
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[chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
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[chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
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[chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
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[chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
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[chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
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[chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
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};
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static int pm8001_id;
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@ -1037,6 +1040,12 @@ static struct pci_device_id pm8001_pci_table[] = {
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{ PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
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{ PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
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{ PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
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{ PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
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{ PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
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{ PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
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{ PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
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{ PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
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{ PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
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{ PCI_VENDOR_ID_ADAPTEC2, 0x8081,
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PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
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{ PCI_VENDOR_ID_ADAPTEC2, 0x8081,
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@ -1057,6 +1066,24 @@ static struct pci_device_id pm8001_pci_table[] = {
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PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
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{ PCI_VENDOR_ID_ADAPTEC2, 0x8089,
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PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
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{ PCI_VENDOR_ID_ADAPTEC2, 0x8074,
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PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
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{ PCI_VENDOR_ID_ADAPTEC2, 0x8076,
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PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
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{ PCI_VENDOR_ID_ADAPTEC2, 0x8077,
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PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
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{ PCI_VENDOR_ID_ADAPTEC2, 0x8074,
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PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
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{ PCI_VENDOR_ID_ADAPTEC2, 0x8076,
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PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
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{ PCI_VENDOR_ID_ADAPTEC2, 0x8077,
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PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
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{ PCI_VENDOR_ID_ADAPTEC2, 0x8076,
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PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
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{ PCI_VENDOR_ID_ADAPTEC2, 0x8077,
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PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
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{ PCI_VENDOR_ID_ADAPTEC2, 0x8074,
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PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
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{} /* terminate list */
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};
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@ -1108,8 +1135,11 @@ module_init(pm8001_init);
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module_exit(pm8001_exit);
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MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
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MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
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MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
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MODULE_DESCRIPTION(
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"PMC-Sierra PM8001/8081/8088/8089 SAS/SATA controller driver");
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"PMC-Sierra PM8001/8081/8088/8089/8074/8076/8077 "
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"SAS/SATA controller driver");
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MODULE_VERSION(DRV_VERSION);
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
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@ -104,6 +104,9 @@ do { \
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#define DEV_IS_EXPANDER(type) ((type == SAS_EDGE_EXPANDER_DEVICE) || (type == SAS_FANOUT_EXPANDER_DEVICE))
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#define IS_SPCV_12G(dev) ((dev->device == 0X8074) \
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|| (dev->device == 0X8076) \
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|| (dev->device == 0X8077))
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#define PM8001_NAME_LENGTH 32/* generic length of strings */
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extern struct list_head hba_list;
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@ -430,7 +430,11 @@ static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
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table is updated */
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pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
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/* wait until Inbound DoorBell Clear Register toggled */
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max_wait_count = 2 * 1000 * 1000;/* 2 sec for spcv/ve */
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if (IS_SPCV_12G(pm8001_ha->pdev)) {
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max_wait_count = 4 * 1000 * 1000;/* 4 sec */
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} else {
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max_wait_count = 2 * 1000 * 1000;/* 2 sec */
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}
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do {
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udelay(1);
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value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
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@ -913,7 +917,11 @@ static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
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pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
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/* wait until Inbound DoorBell Clear Register toggled */
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max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
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if (IS_SPCV_12G(pm8001_ha->pdev)) {
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max_wait_count = 4 * 1000 * 1000;/* 4 sec */
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} else {
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max_wait_count = 2 * 1000 * 1000;/* 2 sec */
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}
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do {
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udelay(1);
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value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
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@ -3941,9 +3949,16 @@ pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
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** [14] 0b disable spin up hold; 1b enable spin up hold
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** [15] ob no change in current PHY analig setup 1b enable using SPAST
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*/
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payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
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LINKMODE_AUTO | LINKRATE_15 |
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LINKRATE_30 | LINKRATE_60 | phy_id);
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if (!IS_SPCV_12G(pm8001_ha->pdev))
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payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
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LINKMODE_AUTO | LINKRATE_15 |
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LINKRATE_30 | LINKRATE_60 | phy_id);
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else
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payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
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LINKMODE_AUTO | LINKRATE_15 |
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LINKRATE_30 | LINKRATE_60 | LINKRATE_120 |
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phy_id);
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/* SSC Disable and SAS Analog ST configuration */
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/**
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payload.ase_sh_lm_slr_phyid =
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@ -168,6 +168,7 @@
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#define LINKRATE_15 (0x01 << 8)
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#define LINKRATE_30 (0x02 << 8)
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#define LINKRATE_60 (0x06 << 8)
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#define LINKRATE_120 (0x08 << 8)
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/* Thermal related */
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#define THERMAL_ENABLE 0x1
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@ -1223,10 +1224,10 @@ typedef struct SASProtocolTimerConfig SASProtocolTimerConfig_t;
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/* MSGU CONFIGURATION TABLE*/
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#define SPCv_MSGU_CFG_TABLE_UPDATE 0x01
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#define SPCv_MSGU_CFG_TABLE_RESET 0x02
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#define SPCv_MSGU_CFG_TABLE_FREEZE 0x04
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#define SPCv_MSGU_CFG_TABLE_UNFREEZE 0x08
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#define SPCv_MSGU_CFG_TABLE_UPDATE 0x001
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#define SPCv_MSGU_CFG_TABLE_RESET 0x002
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#define SPCv_MSGU_CFG_TABLE_FREEZE 0x004
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#define SPCv_MSGU_CFG_TABLE_UNFREEZE 0x008
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#define MSGU_IBDB_SET 0x00
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#define MSGU_HOST_INT_STATUS 0x08
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#define MSGU_HOST_INT_MASK 0x0C
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