- Add G12A Always-On Clock Controller
- Fix Meson8 APB clock ID name -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJcY9seAAoJEHfc29rIyEnRgh8P/1tanqiyRXZIaHDweCMk3WVq +f6e50Kry/54TMZ1jNojsr7r22xHhjFGBy5dkAAXvsrAet0gXmWXtV7M8nE2h0wN mz4h10JVlsyCxa5QDJEKMHP8lGz5Z40C1GVFEZcV/YoHjgeIFgAkeoAhkfh3SLlY T22cSfO1oJ3NRXW5xh+902P+w317zCp0sjJ5RhbxT+30jHy9caA72xpByB6u6gsY 1CmxEA0POtY8JI0VI76ZQRtI+A9S1BGXSIqT2ErCFgPP13DLNzZyk3Hk2bqkpKxj CaP2w7WT8nkhTB00qHfr5Qg7tvamVfdc0ENtLP75VjG7f1UW2qu1ER37KwWYnfDP lv9vB4k+ZeQ7vxbRfi7spkairV7MN5bvECE4yPUaaVe5Uxw6Pf5X5WGvsbeenI/7 xbIy2HaxlmxFljgPwPPWpzAF3whFqGBU30u39drJVyvGxKLfGB619u95F+pPLWD4 +MFSKHzJ6hkgl4/182LYTQ5DrpbRWX6NWOlTUjnIWR+kIaZMj1XZEF/AKBLYBGfS KhrZRgaE8dxPag4RdTu4mQQ/bf3RMKCJQQPoYsOsCr/Z02h2uArwo5dpV0DJX/nS MNV1u5TTlURSlh6CSrBc7u5AjYfgX76rGlGnGSxgHC0P09zTEP5HqZv9GEfc/cIh 8nL7U9wHOM+hHVmE8xNE =/nji -----END PGP SIGNATURE----- Merge tag 'meson-clk-5.1-2' of https://github.com/BayLibre/clk-meson into clk-meson Pull another set of Amlogic clk drivers updates from Neil Armstrong: - Add G12A Always-On Clock Controller - Fix Meson8 APB clock ID name * tag 'meson-clk-5.1-2' of https://github.com/BayLibre/clk-meson: clk: meson: meson8b: fix the naming of the APB clocks dt-bindings: clock: meson8b: add APB clock definition clk: meson: Add G12A AO Clock + Reset Controller dt-bindings: clk: add G12A AO Clock and Reset Bindingshifive-unleashed-5.1
Stephen Boyd
commit
a9ca321716
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@ -10,6 +10,7 @@ Required Properties:
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- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
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- GXM (S912) : "amlogic,meson-gxm-aoclkc"
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- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
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- G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
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followed by the common "amlogic,meson-gx-aoclkc"
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- clocks: list of clock phandle, one for each entry clock-names.
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- clock-names: should contain the following:
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@ -98,8 +98,10 @@ config COMMON_CLK_G12A
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bool
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depends on ARCH_MESON
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select COMMON_CLK_MESON_REGMAP
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select COMMON_CLK_MESON_DUALDIV
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select COMMON_CLK_MESON_MPLL
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select COMMON_CLK_MESON_PLL
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select COMMON_CLK_MESON_AO_CLKC
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select COMMON_CLK_MESON_EE_CLKC
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select MFD_SYSCON
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help
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@ -16,5 +16,5 @@ obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
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obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
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obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
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obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
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obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o
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obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
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obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
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@ -0,0 +1,454 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Amlogic Meson-AXG Clock Controller Driver
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*
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* Copyright (c) 2016 Baylibre SAS.
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* Author: Michael Turquette <mturquette@baylibre.com>
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*
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* Copyright (c) 2019 Baylibre SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/mfd/syscon.h>
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#include "meson-aoclk.h"
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#include "g12a-aoclk.h"
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#include "clk-regmap.h"
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#include "clk-dualdiv.h"
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#define IN_PREFIX "ao-in-"
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/*
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* AO Configuration Clock registers offsets
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* Register offsets from the data sheet must be multiplied by 4.
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*/
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#define AO_RTI_STATUS_REG3 0x0C
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#define AO_RTI_PWR_CNTL_REG0 0x10
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#define AO_RTI_GEN_CNTL_REG0 0x40
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#define AO_CLK_GATE0 0x4c
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#define AO_CLK_GATE0_SP 0x50
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#define AO_OSCIN_CNTL 0x58
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#define AO_CEC_CLK_CNTL_REG0 0x74
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#define AO_CEC_CLK_CNTL_REG1 0x78
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#define AO_SAR_CLK 0x90
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#define AO_RTC_ALT_CLK_CNTL0 0x94
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#define AO_RTC_ALT_CLK_CNTL1 0x98
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/*
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* Like every other peripheral clock gate in Amlogic Clock drivers,
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* we are using CLK_IGNORE_UNUSED here, so we keep the state of the
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* bootloader. The goal is to remove this flag at some point.
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* Actually removing it will require some extensive test to be done safely.
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*/
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#define AXG_AO_GATE(_name, _reg, _bit) \
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static struct clk_regmap g12a_aoclk_##_name = { \
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.data = &(struct clk_regmap_gate_data) { \
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.offset = (_reg), \
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.bit_idx = (_bit), \
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}, \
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.hw.init = &(struct clk_init_data) { \
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.name = "g12a_ao_" #_name, \
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.ops = &clk_regmap_gate_ops, \
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.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \
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.num_parents = 1, \
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.flags = CLK_IGNORE_UNUSED, \
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}, \
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}
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AXG_AO_GATE(ahb, AO_CLK_GATE0, 0);
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AXG_AO_GATE(ir_in, AO_CLK_GATE0, 1);
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AXG_AO_GATE(i2c_m0, AO_CLK_GATE0, 2);
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AXG_AO_GATE(i2c_s0, AO_CLK_GATE0, 3);
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AXG_AO_GATE(uart, AO_CLK_GATE0, 4);
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AXG_AO_GATE(prod_i2c, AO_CLK_GATE0, 5);
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AXG_AO_GATE(uart2, AO_CLK_GATE0, 6);
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AXG_AO_GATE(ir_out, AO_CLK_GATE0, 7);
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AXG_AO_GATE(saradc, AO_CLK_GATE0, 8);
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AXG_AO_GATE(mailbox, AO_CLK_GATE0_SP, 0);
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AXG_AO_GATE(m3, AO_CLK_GATE0_SP, 1);
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AXG_AO_GATE(ahb_sram, AO_CLK_GATE0_SP, 2);
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AXG_AO_GATE(rti, AO_CLK_GATE0_SP, 3);
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AXG_AO_GATE(m4_fclk, AO_CLK_GATE0_SP, 4);
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AXG_AO_GATE(m4_hclk, AO_CLK_GATE0_SP, 5);
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static struct clk_regmap g12a_aoclk_cts_oscin = {
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.data = &(struct clk_regmap_gate_data){
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.offset = AO_RTI_PWR_CNTL_REG0,
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.bit_idx = 14,
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},
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.hw.init = &(struct clk_init_data){
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.name = "cts_oscin",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_names = (const char *[]){ IN_PREFIX "xtal" },
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.num_parents = 1,
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},
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};
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static const struct meson_clk_dualdiv_param g12a_32k_div_table[] = {
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{
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.dual = 1,
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.n1 = 733,
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.m1 = 8,
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.n2 = 732,
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.m2 = 11,
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}, {}
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};
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/* 32k_by_oscin clock */
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static struct clk_regmap g12a_aoclk_32k_by_oscin_pre = {
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.data = &(struct clk_regmap_gate_data){
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.offset = AO_RTC_ALT_CLK_CNTL0,
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.bit_idx = 31,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_32k_by_oscin_pre",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "cts_oscin" },
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.num_parents = 1,
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},
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};
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static struct clk_regmap g12a_aoclk_32k_by_oscin_div = {
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.data = &(struct meson_clk_dualdiv_data){
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.n1 = {
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.reg_off = AO_RTC_ALT_CLK_CNTL0,
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.shift = 0,
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.width = 12,
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},
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.n2 = {
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.reg_off = AO_RTC_ALT_CLK_CNTL0,
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.shift = 12,
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.width = 12,
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},
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.m1 = {
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.reg_off = AO_RTC_ALT_CLK_CNTL1,
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.shift = 0,
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.width = 12,
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},
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.m2 = {
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.reg_off = AO_RTC_ALT_CLK_CNTL1,
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.shift = 12,
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.width = 12,
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},
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.dual = {
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.reg_off = AO_RTC_ALT_CLK_CNTL0,
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.shift = 28,
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.width = 1,
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},
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.table = g12a_32k_div_table,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_32k_by_oscin_div",
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.ops = &meson_clk_dualdiv_ops,
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.parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_pre" },
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.num_parents = 1,
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},
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};
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static struct clk_regmap g12a_aoclk_32k_by_oscin_sel = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_RTC_ALT_CLK_CNTL1,
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.mask = 0x1,
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.shift = 24,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_32k_by_oscin_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_div",
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"g12a_ao_32k_by_oscin_pre" },
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_aoclk_32k_by_oscin = {
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.data = &(struct clk_regmap_gate_data){
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.offset = AO_RTC_ALT_CLK_CNTL0,
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.bit_idx = 30,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_32k_by_oscin",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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/* cec clock */
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static struct clk_regmap g12a_aoclk_cec_pre = {
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.data = &(struct clk_regmap_gate_data){
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.offset = AO_CEC_CLK_CNTL_REG0,
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.bit_idx = 31,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_cec_pre",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "cts_oscin" },
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.num_parents = 1,
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},
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};
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static struct clk_regmap g12a_aoclk_cec_div = {
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.data = &(struct meson_clk_dualdiv_data){
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.n1 = {
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.reg_off = AO_CEC_CLK_CNTL_REG0,
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.shift = 0,
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.width = 12,
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},
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.n2 = {
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.reg_off = AO_CEC_CLK_CNTL_REG0,
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.shift = 12,
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.width = 12,
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},
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.m1 = {
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.reg_off = AO_CEC_CLK_CNTL_REG1,
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.shift = 0,
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.width = 12,
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},
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.m2 = {
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.reg_off = AO_CEC_CLK_CNTL_REG1,
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.shift = 12,
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.width = 12,
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},
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.dual = {
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.reg_off = AO_CEC_CLK_CNTL_REG0,
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.shift = 28,
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.width = 1,
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},
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.table = g12a_32k_div_table,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_cec_div",
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.ops = &meson_clk_dualdiv_ops,
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.parent_names = (const char *[]){ "g12a_ao_cec_pre" },
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.num_parents = 1,
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},
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};
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static struct clk_regmap g12a_aoclk_cec_sel = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_CEC_CLK_CNTL_REG1,
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.mask = 0x1,
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.shift = 24,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_cec_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = (const char *[]){ "g12a_ao_cec_div",
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"g12a_ao_cec_pre" },
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_aoclk_cec = {
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.data = &(struct clk_regmap_gate_data){
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.offset = AO_CEC_CLK_CNTL_REG0,
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.bit_idx = 30,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_cec",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "g12a_ao_cec_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_aoclk_cts_rtc_oscin = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_RTI_PWR_CNTL_REG0,
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.mask = 0x1,
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.shift = 10,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_cts_rtc_oscin",
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.ops = &clk_regmap_mux_ops,
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.parent_names = (const char *[]){ "g12a_ao_32k_by_oscin",
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IN_PREFIX "ext_32k-0" },
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_aoclk_clk81 = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_RTI_PWR_CNTL_REG0,
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.mask = 0x1,
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.shift = 8,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_clk81",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk",
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"g12a_ao_cts_rtc_oscin"},
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_aoclk_saradc_mux = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_SAR_CLK,
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.mask = 0x3,
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.shift = 9,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_saradc_mux",
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.ops = &clk_regmap_mux_ops,
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.parent_names = (const char *[]){ IN_PREFIX "xtal",
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"g12a_ao_clk81" },
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.num_parents = 2,
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},
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};
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static struct clk_regmap g12a_aoclk_saradc_div = {
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.data = &(struct clk_regmap_div_data) {
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.offset = AO_SAR_CLK,
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.shift = 0,
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.width = 8,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_saradc_div",
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "g12a_ao_saradc_mux" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap g12a_aoclk_saradc_gate = {
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.data = &(struct clk_regmap_gate_data) {
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.offset = AO_SAR_CLK,
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.bit_idx = 8,
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},
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.hw.init = &(struct clk_init_data){
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.name = "g12a_ao_saradc_gate",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "g12a_ao_saradc_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static const unsigned int g12a_aoclk_reset[] = {
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[RESET_AO_IR_IN] = 16,
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[RESET_AO_UART] = 17,
|
||||
[RESET_AO_I2C_M] = 18,
|
||||
[RESET_AO_I2C_S] = 19,
|
||||
[RESET_AO_SAR_ADC] = 20,
|
||||
[RESET_AO_UART2] = 22,
|
||||
[RESET_AO_IR_OUT] = 23,
|
||||
};
|
||||
|
||||
static struct clk_regmap *g12a_aoclk_regmap[] = {
|
||||
&g12a_aoclk_ahb,
|
||||
&g12a_aoclk_ir_in,
|
||||
&g12a_aoclk_i2c_m0,
|
||||
&g12a_aoclk_i2c_s0,
|
||||
&g12a_aoclk_uart,
|
||||
&g12a_aoclk_prod_i2c,
|
||||
&g12a_aoclk_uart2,
|
||||
&g12a_aoclk_ir_out,
|
||||
&g12a_aoclk_saradc,
|
||||
&g12a_aoclk_mailbox,
|
||||
&g12a_aoclk_m3,
|
||||
&g12a_aoclk_ahb_sram,
|
||||
&g12a_aoclk_rti,
|
||||
&g12a_aoclk_m4_fclk,
|
||||
&g12a_aoclk_m4_hclk,
|
||||
&g12a_aoclk_cts_oscin,
|
||||
&g12a_aoclk_32k_by_oscin_pre,
|
||||
&g12a_aoclk_32k_by_oscin_div,
|
||||
&g12a_aoclk_32k_by_oscin_sel,
|
||||
&g12a_aoclk_32k_by_oscin,
|
||||
&g12a_aoclk_cec_pre,
|
||||
&g12a_aoclk_cec_div,
|
||||
&g12a_aoclk_cec_sel,
|
||||
&g12a_aoclk_cec,
|
||||
&g12a_aoclk_cts_rtc_oscin,
|
||||
&g12a_aoclk_clk81,
|
||||
&g12a_aoclk_saradc_mux,
|
||||
&g12a_aoclk_saradc_div,
|
||||
&g12a_aoclk_saradc_gate,
|
||||
};
|
||||
|
||||
static const struct clk_hw_onecell_data g12a_aoclk_onecell_data = {
|
||||
.hws = {
|
||||
[CLKID_AO_AHB] = &g12a_aoclk_ahb.hw,
|
||||
[CLKID_AO_IR_IN] = &g12a_aoclk_ir_in.hw,
|
||||
[CLKID_AO_I2C_M0] = &g12a_aoclk_i2c_m0.hw,
|
||||
[CLKID_AO_I2C_S0] = &g12a_aoclk_i2c_s0.hw,
|
||||
[CLKID_AO_UART] = &g12a_aoclk_uart.hw,
|
||||
[CLKID_AO_PROD_I2C] = &g12a_aoclk_prod_i2c.hw,
|
||||
[CLKID_AO_UART2] = &g12a_aoclk_uart2.hw,
|
||||
[CLKID_AO_IR_OUT] = &g12a_aoclk_ir_out.hw,
|
||||
[CLKID_AO_SAR_ADC] = &g12a_aoclk_saradc.hw,
|
||||
[CLKID_AO_MAILBOX] = &g12a_aoclk_mailbox.hw,
|
||||
[CLKID_AO_M3] = &g12a_aoclk_m3.hw,
|
||||
[CLKID_AO_AHB_SRAM] = &g12a_aoclk_ahb_sram.hw,
|
||||
[CLKID_AO_RTI] = &g12a_aoclk_rti.hw,
|
||||
[CLKID_AO_M4_FCLK] = &g12a_aoclk_m4_fclk.hw,
|
||||
[CLKID_AO_M4_HCLK] = &g12a_aoclk_m4_hclk.hw,
|
||||
[CLKID_AO_CLK81] = &g12a_aoclk_clk81.hw,
|
||||
[CLKID_AO_SAR_ADC_SEL] = &g12a_aoclk_saradc_mux.hw,
|
||||
[CLKID_AO_SAR_ADC_DIV] = &g12a_aoclk_saradc_div.hw,
|
||||
[CLKID_AO_SAR_ADC_CLK] = &g12a_aoclk_saradc_gate.hw,
|
||||
[CLKID_AO_CTS_OSCIN] = &g12a_aoclk_cts_oscin.hw,
|
||||
[CLKID_AO_32K_PRE] = &g12a_aoclk_32k_by_oscin_pre.hw,
|
||||
[CLKID_AO_32K_DIV] = &g12a_aoclk_32k_by_oscin_div.hw,
|
||||
[CLKID_AO_32K_SEL] = &g12a_aoclk_32k_by_oscin_sel.hw,
|
||||
[CLKID_AO_32K] = &g12a_aoclk_32k_by_oscin.hw,
|
||||
[CLKID_AO_CEC_PRE] = &g12a_aoclk_cec_pre.hw,
|
||||
[CLKID_AO_CEC_DIV] = &g12a_aoclk_cec_div.hw,
|
||||
[CLKID_AO_CEC_SEL] = &g12a_aoclk_cec_sel.hw,
|
||||
[CLKID_AO_CEC] = &g12a_aoclk_cec.hw,
|
||||
[CLKID_AO_CTS_RTC_OSCIN] = &g12a_aoclk_cts_rtc_oscin.hw,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
};
|
||||
|
||||
static const struct meson_aoclk_input g12a_aoclk_inputs[] = {
|
||||
{ .name = "xtal", .required = true },
|
||||
{ .name = "mpeg-clk", .required = true },
|
||||
{ .name = "ext-32k-0", .required = false },
|
||||
};
|
||||
|
||||
static const struct meson_aoclk_data g12a_aoclkc_data = {
|
||||
.reset_reg = AO_RTI_GEN_CNTL_REG0,
|
||||
.num_reset = ARRAY_SIZE(g12a_aoclk_reset),
|
||||
.reset = g12a_aoclk_reset,
|
||||
.num_clks = ARRAY_SIZE(g12a_aoclk_regmap),
|
||||
.clks = g12a_aoclk_regmap,
|
||||
.hw_data = &g12a_aoclk_onecell_data,
|
||||
.inputs = g12a_aoclk_inputs,
|
||||
.num_inputs = ARRAY_SIZE(g12a_aoclk_inputs),
|
||||
.input_prefix = IN_PREFIX,
|
||||
};
|
||||
|
||||
static const struct of_device_id g12a_aoclkc_match_table[] = {
|
||||
{
|
||||
.compatible = "amlogic,meson-g12a-aoclkc",
|
||||
.data = &g12a_aoclkc_data,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver g12a_aoclkc_driver = {
|
||||
.probe = meson_aoclkc_probe,
|
||||
.driver = {
|
||||
.name = "g12a-aoclkc",
|
||||
.of_match_table = g12a_aoclkc_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(g12a_aoclkc_driver);
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2019 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef __G12A_AOCLKC_H
|
||||
#define __G12A_AOCLKC_H
|
||||
|
||||
/*
|
||||
* CLKID index values
|
||||
*
|
||||
* These indices are entirely contrived and do not map onto the hardware.
|
||||
* It has now been decided to expose everything by default in the DT header:
|
||||
* include/dt-bindings/clock/g12a-aoclkc.h. Only the clocks ids we don't want
|
||||
* to expose, such as the internal muxes and dividers of composite clocks,
|
||||
* will remain defined here.
|
||||
*/
|
||||
#define CLKID_AO_SAR_ADC_SEL 16
|
||||
#define CLKID_AO_SAR_ADC_DIV 17
|
||||
#define CLKID_AO_CTS_OSCIN 19
|
||||
#define CLKID_AO_32K_PRE 20
|
||||
#define CLKID_AO_32K_DIV 21
|
||||
#define CLKID_AO_32K_SEL 22
|
||||
#define CLKID_AO_CEC_PRE 24
|
||||
#define CLKID_AO_CEC_DIV 25
|
||||
#define CLKID_AO_CEC_SEL 26
|
||||
|
||||
#define NR_CLKS 29
|
||||
|
||||
#include <dt-bindings/clock/g12a-aoclkc.h>
|
||||
#include <dt-bindings/reset/g12a-aoclkc.h>
|
||||
|
||||
#endif /* __G12A_AOCLKC_H */
|
||||
|
|
@ -804,16 +804,16 @@ static struct clk_fixed_factor meson8b_cpu_clk_div8 = {
|
|||
},
|
||||
};
|
||||
|
||||
static u32 mux_table_abp[] = { 1, 2, 3, 4, 5, 6, 7 };
|
||||
static struct clk_regmap meson8b_abp_clk_sel = {
|
||||
static u32 mux_table_apb[] = { 1, 2, 3, 4, 5, 6, 7 };
|
||||
static struct clk_regmap meson8b_apb_clk_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL1,
|
||||
.mask = 0x7,
|
||||
.shift = 3,
|
||||
.table = mux_table_abp,
|
||||
.table = mux_table_apb,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "abp_clk_sel",
|
||||
.name = "apb_clk_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk_div2",
|
||||
"cpu_clk_div3",
|
||||
|
|
@ -826,16 +826,16 @@ static struct clk_regmap meson8b_abp_clk_sel = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_abp_clk_gate = {
|
||||
static struct clk_regmap meson8b_apb_clk_gate = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL1,
|
||||
.bit_idx = 16,
|
||||
.flags = CLK_GATE_SET_TO_DISABLE,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "abp_clk_dis",
|
||||
.name = "apb_clk_dis",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_names = (const char *[]){ "abp_clk_sel" },
|
||||
.parent_names = (const char *[]){ "apb_clk_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
|
|
@ -1911,8 +1911,8 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
|
|||
[CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
|
||||
[CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
|
||||
[CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
|
||||
[CLKID_ABP_SEL] = &meson8b_abp_clk_sel.hw,
|
||||
[CLKID_ABP] = &meson8b_abp_clk_gate.hw,
|
||||
[CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
|
||||
[CLKID_APB] = &meson8b_apb_clk_gate.hw,
|
||||
[CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
|
||||
[CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
|
||||
[CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
|
||||
|
|
@ -2093,8 +2093,8 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
|
|||
[CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
|
||||
[CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
|
||||
[CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
|
||||
[CLKID_ABP_SEL] = &meson8b_abp_clk_sel.hw,
|
||||
[CLKID_ABP] = &meson8b_abp_clk_gate.hw,
|
||||
[CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
|
||||
[CLKID_APB] = &meson8b_apb_clk_gate.hw,
|
||||
[CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
|
||||
[CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
|
||||
[CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
|
||||
|
|
@ -2262,8 +2262,8 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
|
|||
&meson8b_fixed_pll_dco,
|
||||
&meson8b_hdmi_pll_dco,
|
||||
&meson8b_sys_pll_dco,
|
||||
&meson8b_abp_clk_sel,
|
||||
&meson8b_abp_clk_gate,
|
||||
&meson8b_apb_clk_sel,
|
||||
&meson8b_apb_clk_gate,
|
||||
&meson8b_periph_clk_sel,
|
||||
&meson8b_periph_clk_gate,
|
||||
&meson8b_axi_clk_sel,
|
||||
|
|
|
|||
|
|
@ -92,7 +92,7 @@
|
|||
#define CLKID_CPU_CLK_DIV6 120
|
||||
#define CLKID_CPU_CLK_DIV7 121
|
||||
#define CLKID_CPU_CLK_DIV8 122
|
||||
#define CLKID_ABP_SEL 123
|
||||
#define CLKID_APB_SEL 123
|
||||
#define CLKID_PERIPH_SEL 125
|
||||
#define CLKID_AXI_SEL 127
|
||||
#define CLKID_L2_DRAM_SEL 129
|
||||
|
|
|
|||
|
|
@ -0,0 +1,34 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2016 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* Copyright (c) 2018 Amlogic, inc.
|
||||
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
|
||||
*/
|
||||
|
||||
#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
|
||||
#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
|
||||
|
||||
#define CLKID_AO_AHB 0
|
||||
#define CLKID_AO_IR_IN 1
|
||||
#define CLKID_AO_I2C_M0 2
|
||||
#define CLKID_AO_I2C_S0 3
|
||||
#define CLKID_AO_UART 4
|
||||
#define CLKID_AO_PROD_I2C 5
|
||||
#define CLKID_AO_UART2 6
|
||||
#define CLKID_AO_IR_OUT 7
|
||||
#define CLKID_AO_SAR_ADC 8
|
||||
#define CLKID_AO_MAILBOX 9
|
||||
#define CLKID_AO_M3 10
|
||||
#define CLKID_AO_AHB_SRAM 11
|
||||
#define CLKID_AO_RTI 12
|
||||
#define CLKID_AO_M4_FCLK 13
|
||||
#define CLKID_AO_M4_HCLK 14
|
||||
#define CLKID_AO_CLK81 15
|
||||
#define CLKID_AO_SAR_ADC_CLK 18
|
||||
#define CLKID_AO_32K 23
|
||||
#define CLKID_AO_CEC 27
|
||||
#define CLKID_AO_CTS_RTC_OSCIN 28
|
||||
|
||||
#endif
|
||||
|
|
@ -104,6 +104,7 @@
|
|||
#define CLKID_MPLL2 95
|
||||
#define CLKID_NAND_CLK 112
|
||||
#define CLKID_ABP 124
|
||||
#define CLKID_APB 124
|
||||
#define CLKID_PERIPH 126
|
||||
#define CLKID_AXI 128
|
||||
#define CLKID_L2_DRAM 130
|
||||
|
|
|
|||
|
|
@ -0,0 +1,18 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2016 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK
|
||||
#define DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK
|
||||
|
||||
#define RESET_AO_IR_IN 0
|
||||
#define RESET_AO_UART 1
|
||||
#define RESET_AO_I2C_M 2
|
||||
#define RESET_AO_I2C_S 3
|
||||
#define RESET_AO_SAR_ADC 4
|
||||
#define RESET_AO_UART2 5
|
||||
#define RESET_AO_IR_OUT 6
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue