rtlwifi: Make changes in rtlwifi/rtl8192ce/reg.h to support rtl8192cu
This change modifies rtlwifi/rtl8192ce/reg.h to support rtl8192cu. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>hifive-unleashed-5.1
Larry Finger
John W. Linville
parent
69081624c7
commit
a9dd591919
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@ -63,7 +63,15 @@
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#define REG_LEDCFG3 0x004F
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#define REG_FSIMR 0x0050
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#define REG_FSISR 0x0054
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#define REG_HSIMR 0x0058
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#define REG_HSISR 0x005c
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/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
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#define REG_GPIO_PIN_CTRL_2 0x0060
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/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
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#define REG_GPIO_IO_SEL_2 0x0062
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/* RTL8723 WIFI/BT/GPS Multi-Function control source. */
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#define REG_MULTI_FUNC_CTRL 0x0068
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#define REG_MCUFWDL 0x0080
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#define REG_HMEBOX_EXT_0 0x0088
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@ -79,6 +87,7 @@
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#define REG_PCIE_MIO_INTD 0x00E8
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#define REG_HPON_FSM 0x00EC
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#define REG_SYS_CFG 0x00F0
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#define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only.*/
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#define REG_CR 0x0100
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#define REG_PBP 0x0104
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@ -209,6 +218,8 @@
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#define REG_RDG_PIFS 0x0513
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#define REG_SIFS_CTX 0x0514
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#define REG_SIFS_TRX 0x0516
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#define REG_SIFS_CCK 0x0514
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#define REG_SIFS_OFDM 0x0516
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#define REG_AGGR_BREAK_TIME 0x051A
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#define REG_SLOT 0x051B
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#define REG_TX_PTCL_CTRL 0x0520
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@ -261,6 +272,10 @@
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#define REG_MAC_SPEC_SIFS 0x063A
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#define REG_RESP_SIFS_CCK 0x063C
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#define REG_RESP_SIFS_OFDM 0x063E
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/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */
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#define REG_R2T_SIFS 0x063C
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/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */
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#define REG_T2T_SIFS 0x063E
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#define REG_ACKTO 0x0640
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#define REG_CTS2TO 0x0641
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#define REG_EIFS 0x0642
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@ -641,9 +656,10 @@
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#define STOPBE BIT(1)
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#define STOPBK BIT(0)
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#define RCR_APPFCS BIT(31)
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#define RCR_APP_FCS BIT(31)
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#define RCR_APP_MIC BIT(30)
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#define RCR_APP_ICV BIT(29)
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#define RCR_APP_PHYSTS BIT(28)
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#define RCR_APP_PHYST_RXFF BIT(28)
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#define RCR_APP_BA_SSN BIT(27)
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#define RCR_ENMBID BIT(24)
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@ -759,6 +775,7 @@
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#define BOOT_FROM_EEPROM BIT(4)
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#define EEPROM_EN BIT(5)
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#define EEPROMSEL BOOT_FROM_EEPROM
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#define AFE_BGEN BIT(0)
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#define AFE_MBEN BIT(1)
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@ -876,6 +893,8 @@
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#define BD_MAC2 BIT(9)
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#define BD_MAC1 BIT(10)
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#define IC_MACPHY_MODE BIT(11)
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#define BT_FUNC BIT(16)
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#define VENDOR_ID BIT(19)
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#define PAD_HWPD_IDN BIT(22)
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#define TRP_VAUX_EN BIT(23)
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#define TRP_BT_EN BIT(24)
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@ -883,6 +902,28 @@
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#define BD_HCI_SEL BIT(26)
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#define TYPE_ID BIT(27)
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/* REG_GPIO_OUTSTS (For RTL8723 only) */
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#define EFS_HCI_SEL (BIT(0)|BIT(1))
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#define PAD_HCI_SEL (BIT(2)|BIT(3))
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#define HCI_SEL (BIT(4)|BIT(5))
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#define PKG_SEL_HCI BIT(6)
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#define FEN_GPS BIT(7)
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#define FEN_BT BIT(8)
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#define FEN_WL BIT(9)
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#define FEN_PCI BIT(10)
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#define FEN_USB BIT(11)
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#define BTRF_HWPDN_N BIT(12)
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#define WLRF_HWPDN_N BIT(13)
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#define PDN_BT_N BIT(14)
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#define PDN_GPS_N BIT(15)
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#define BT_CTL_HWPDN BIT(16)
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#define GPS_CTL_HWPDN BIT(17)
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#define PPHY_SUSB BIT(20)
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#define UPHY_SUSB BIT(21)
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#define PCI_SUSEN BIT(22)
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#define USB_SUSEN BIT(23)
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#define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
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#define CHIP_VER_RTL_MASK 0xF000
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#define CHIP_VER_RTL_SHIFT 12
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@ -1184,6 +1225,30 @@
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#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)
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/* REG_MULTI_FUNC_CTRL(For RTL8723 Only) */
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/* Enable GPIO[9] as WiFi HW PDn source */
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#define WL_HWPDN_EN BIT(0)
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/* WiFi HW PDn polarity control */
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#define WL_HWPDN_SL BIT(1)
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/* WiFi function enable */
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#define WL_FUNC_EN BIT(2)
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/* Enable GPIO[9] as WiFi RF HW PDn source */
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#define WL_HWROF_EN BIT(3)
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/* Enable GPIO[11] as BT HW PDn source */
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#define BT_HWPDN_EN BIT(16)
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/* BT HW PDn polarity control */
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#define BT_HWPDN_SL BIT(17)
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/* BT function enable */
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#define BT_FUNC_EN BIT(18)
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/* Enable GPIO[11] as BT/GPS RF HW PDn source */
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#define BT_HWROF_EN BIT(19)
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/* Enable GPIO[10] as GPS HW PDn source */
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#define GPS_HWPDN_EN BIT(20)
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/* GPS HW PDn polarity control */
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#define GPS_HWPDN_SL BIT(21)
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/* GPS function enable */
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#define GPS_FUNC_EN BIT(22)
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#define RPMAC_RESET 0x100
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#define RPMAC_TXSTART 0x104
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#define RPMAC_TXLEGACYSIG 0x108
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@ -1496,7 +1561,7 @@
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#define BTXHTSTBC 0x30
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#define BTXHTADVANCECODING 0x40
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#define BTXHTSHORTGI 0x80
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#define BTXHTNUMBERHT_LT F 0x300
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#define BTXHTNUMBERHT_LTF 0x300
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#define BTXHTCRC8 0x3fc00
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#define BCOUNTERRESET 0x10000
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#define BNUMOFOFDMTX 0xffff
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@ -52,7 +52,7 @@ int rtl92c_init_sw_vars(struct ieee80211_hw *hw)
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rtlpriv->dm.thermalvalue = 0;
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rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
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rtlpci->receive_config = (RCR_APPFCS |
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rtlpci->receive_config = (RCR_APP_FCS |
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RCR_AMF |
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RCR_ADF |
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RCR_APP_MIC |
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