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cpufreq: imx6q: keep PLL1 enabled from bypassed clock when NOT used 

For some i.MX platforms such as i.MX6SX, PLL1 is used as temporary
clock during low power idle mode enter/exit, it MUST be enabled, but
can be switch to its default bypass clock source OSC. This patch
adds support for such scenario, when PLL1 is NOT used, bypass it and
keep it enabled.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Anson Huang 2019-04-18 16:00:09 +08:00 committed by Dong Aisheng
parent 48396c917a
commit a9e5893d31
1 changed files with 15 additions and 2 deletions
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17
drivers/cpufreq/imx6q-cpufreq.c
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@ -31,12 +31,15 @@ enum IMX6_CPUFREQ_CLKS {
STEP,
PLL1_SW,
PLL2_PFD2_396M,
PLL1,
PLL1_BYPASS,
PLL1_BYPASS_SRC,
/* MX6UL requires two more clks */
PLL2_BUS,
SECONDARY_SEL,
};
#define IMX6Q_CPUFREQ_CLK_NUM 5
#define IMX6UL_CPUFREQ_CLK_NUM 7
#define IMX6Q_CPUFREQ_CLK_NUM 8
#define IMX6UL_CPUFREQ_CLK_NUM 10
static int num_clks;
static struct clk_bulk_data clks[] = {
@ -45,6 +48,9 @@ static struct clk_bulk_data clks[] = {
{ .id = "step" },
{ .id = "pll1_sw" },
{ .id = "pll2_pfd2_396m" },
{ .id = "pll1" },
{ .id = "pll1_bypass" },
{ .id = "pll1_bypass_src" },
{ .id = "pll2_bus" },
{ .id = "secondary_sel" },
};
@ -148,11 +154,18 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
/* Ensure that pll1_bypass is set back to
* pll1. We have to do this first so that the
* change rate done to pll1_sys_clk done below
* can propagate up to pll1.
*/
clk_set_parent(clks[PLL1_BYPASS].clk, clks[PLL1].clk);
clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
} else {
/* pll1_sys needs to be enabled for divider rate change to work. */
pll1_sys_temp_enabled = true;
clk_set_parent(clks[PLL1_BYPASS].clk, clks[PLL1_BYPASS_SRC].clk);
clk_prepare_enable(clks[PLL1_SYS].clk);
}
}