ARM: S5PV210: Add SCLK_SPDIF clock
This patch add SCLK_SPDIF clock to support source clock of S/PDIF on S5PV210. Signed-off-by: Seungwhan Youn <sw.youn@samsung.com> Acked-by: Jassi Brar <jassi.brar@samsung.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -472,6 +472,12 @@ static struct clk init_clocks_disable[] = {
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.parent = &clk_p,
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.parent = &clk_p,
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.enable = s5pv210_clk_ip3_ctrl,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1 << 6),
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.ctrlbit = (1 << 6),
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}, {
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.name = "spdif",
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.id = -1,
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.parent = &clk_p,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1 << 0),
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},
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},
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};
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};
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@ -701,6 +707,53 @@ static struct clksrc_sources clkset_sclk_spdif = {
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.nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
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.nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
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};
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};
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static int s5pv210_spdif_set_rate(struct clk *clk, unsigned long rate)
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{
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struct clk *pclk;
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int ret;
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pclk = clk_get_parent(clk);
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if (IS_ERR(pclk))
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return -EINVAL;
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ret = pclk->ops->set_rate(pclk, rate);
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clk_put(pclk);
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return ret;
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}
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static unsigned long s5pv210_spdif_get_rate(struct clk *clk)
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{
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struct clk *pclk;
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int rate;
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pclk = clk_get_parent(clk);
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if (IS_ERR(pclk))
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return -EINVAL;
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rate = pclk->ops->get_rate(clk);
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clk_put(pclk);
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return rate;
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}
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static struct clk_ops s5pv210_sclk_spdif_ops = {
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.set_rate = s5pv210_spdif_set_rate,
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.get_rate = s5pv210_spdif_get_rate,
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};
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static struct clksrc_clk clk_sclk_spdif = {
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.clk = {
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.name = "sclk_spdif",
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.id = -1,
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 27),
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.ops = &s5pv210_sclk_spdif_ops,
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},
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.sources = &clkset_sclk_spdif,
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.reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
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};
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static struct clk *clkset_group2_list[] = {
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static struct clk *clkset_group2_list[] = {
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[0] = &clk_ext_xtal_mux,
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[0] = &clk_ext_xtal_mux,
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[1] = &clk_xusbxti,
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[1] = &clk_xusbxti,
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@ -784,15 +837,6 @@ static struct clksrc_clk clksrcs[] = {
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},
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},
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.sources = &clkset_sclk_mixer,
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.sources = &clkset_sclk_mixer,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
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}, {
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.clk = {
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.name = "sclk_spdif",
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.id = -1,
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 27),
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},
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.sources = &clkset_sclk_spdif,
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.reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
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}, {
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}, {
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.clk = {
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.clk = {
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.name = "sclk_fimc",
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.name = "sclk_fimc",
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