clk: mmp2: Fix the order of timer mux parents
[ Upstream commit5.4-rM2-2.2.x-imx-squashed8bea5ac0fb
] Determined empirically, no documentation is available. The OLPC XO-1.75 laptop used parent 1, that one being VCTCXO/4 (65MHz), but thought it's a VCTCXO/2 (130MHz). The mmp2 timer driver, not knowing what is going on, ended up just dividing the rate as of commitf36797ee43
("ARM: mmp/mmp2: dt: enable the clock")' Link: https://lore.kernel.org/r/20191218190454.420358-3-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -134,7 +134,7 @@ static DEFINE_SPINLOCK(ssp3_lock);
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static const char *ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
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static DEFINE_SPINLOCK(timer_lock);
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static const char *timer_parent_names[] = {"clk32", "vctcxo_2", "vctcxo_4", "vctcxo"};
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static const char *timer_parent_names[] = {"clk32", "vctcxo_4", "vctcxo_2", "vctcxo"};
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static DEFINE_SPINLOCK(reset_lock);
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