intel_th: msu: Start handling IRQs
We intend to use the interrupt to detect Last Block condition in the MSU driver, which we can use for double-buffering software-managed data transfers. Add an interrupt handler to the MSU driver. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>hifive-unleashed-5.2
Alexander Shishkin
Greg Kroah-Hartman
parent
7b7036d47c
commit
aac8da6517
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@ -826,6 +826,28 @@ static const struct file_operations intel_th_output_fops = {
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.llseek = noop_llseek,
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};
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static irqreturn_t intel_th_irq(int irq, void *data)
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{
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struct intel_th *th = data;
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irqreturn_t ret = IRQ_NONE;
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struct intel_th_driver *d;
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int i;
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for (i = 0; i < th->num_thdevs; i++) {
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if (th->thdev[i]->type != INTEL_TH_OUTPUT)
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continue;
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d = to_intel_th_driver(th->thdev[i]->dev.driver);
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if (d && d->irq)
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ret |= d->irq(th->thdev[i]);
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}
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if (ret == IRQ_NONE)
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pr_warn_ratelimited("nobody cared for irq\n");
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return ret;
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}
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/**
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* intel_th_alloc() - allocate a new Intel TH device and its subdevices
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* @dev: parent device
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@ -865,6 +887,12 @@ intel_th_alloc(struct device *dev, struct intel_th_drvdata *drvdata,
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th->resource[nr_mmios++] = devres[r];
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break;
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case IORESOURCE_IRQ:
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err = devm_request_irq(dev, devres[r].start,
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intel_th_irq, IRQF_SHARED,
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dev_name(dev), th);
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if (err)
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goto err_chrdev;
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if (th->irq == -1)
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th->irq = devres[r].start;
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break;
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@ -891,6 +919,10 @@ intel_th_alloc(struct device *dev, struct intel_th_drvdata *drvdata,
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return th;
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err_chrdev:
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__unregister_chrdev(th->major, 0, TH_POSSIBLE_OUTPUTS,
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"intel_th/output");
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err_ida:
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ida_simple_remove(&intel_th_ida, th->id);
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@ -8,6 +8,8 @@
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#ifndef __INTEL_TH_H__
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#define __INTEL_TH_H__
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#include <linux/irqreturn.h>
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/* intel_th_device device types */
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enum {
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/* Devices that generate trace data */
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@ -160,7 +162,7 @@ struct intel_th_driver {
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void (*disable)(struct intel_th_device *thdev,
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struct intel_th_output *output);
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/* output ops */
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void (*irq)(struct intel_th_device *thdev);
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irqreturn_t (*irq)(struct intel_th_device *thdev);
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int (*activate)(struct intel_th_device *thdev);
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void (*deactivate)(struct intel_th_device *thdev);
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/* file_operations for those who want a device node */
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@ -102,6 +102,7 @@ struct msc_iter {
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*/
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struct msc {
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void __iomem *reg_base;
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void __iomem *msu_base;
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struct intel_th_device *thdev;
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struct list_head win_list;
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@ -122,7 +123,8 @@ struct msc {
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/* config */
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unsigned int enabled : 1,
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wrap : 1;
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wrap : 1,
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do_irq : 1;
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unsigned int mode;
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unsigned int burst_len;
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unsigned int index;
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@ -476,6 +478,40 @@ static void msc_buffer_clear_hw_header(struct msc *msc)
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}
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}
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static int intel_th_msu_init(struct msc *msc)
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{
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u32 mintctl, msusts;
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if (!msc->do_irq)
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return 0;
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mintctl = ioread32(msc->msu_base + REG_MSU_MINTCTL);
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mintctl |= msc->index ? M1BLIE : M0BLIE;
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iowrite32(mintctl, msc->msu_base + REG_MSU_MINTCTL);
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if (mintctl != ioread32(msc->msu_base + REG_MSU_MINTCTL)) {
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dev_info(msc_dev(msc), "MINTCTL ignores writes: no usable interrupts\n");
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msc->do_irq = 0;
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return 0;
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}
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msusts = ioread32(msc->msu_base + REG_MSU_MSUSTS);
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iowrite32(msusts, msc->msu_base + REG_MSU_MSUSTS);
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return 0;
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}
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static void intel_th_msu_deinit(struct msc *msc)
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{
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u32 mintctl;
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if (!msc->do_irq)
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return;
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mintctl = ioread32(msc->msu_base + REG_MSU_MINTCTL);
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mintctl &= msc->index ? ~M1BLIE : ~M0BLIE;
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iowrite32(mintctl, msc->msu_base + REG_MSU_MINTCTL);
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}
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/**
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* msc_configure() - set up MSC hardware
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* @msc: the MSC device to configure
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@ -1295,6 +1331,21 @@ static int intel_th_msc_init(struct msc *msc)
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return 0;
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}
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static irqreturn_t intel_th_msc_interrupt(struct intel_th_device *thdev)
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{
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struct msc *msc = dev_get_drvdata(&thdev->dev);
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u32 msusts = ioread32(msc->msu_base + REG_MSU_MSUSTS);
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u32 mask = msc->index ? MSUSTS_MSC1BLAST : MSUSTS_MSC0BLAST;
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if (!(msusts & mask)) {
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if (msc->enabled)
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return IRQ_HANDLED;
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return IRQ_NONE;
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}
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return IRQ_HANDLED;
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}
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static const char * const msc_mode[] = {
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[MSC_MODE_SINGLE] = "single",
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[MSC_MODE_MULTI] = "multi",
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@ -1500,10 +1551,19 @@ static int intel_th_msc_probe(struct intel_th_device *thdev)
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if (!msc)
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return -ENOMEM;
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res = intel_th_device_get_resource(thdev, IORESOURCE_IRQ, 1);
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if (!res)
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msc->do_irq = 1;
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msc->index = thdev->id;
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msc->thdev = thdev;
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msc->reg_base = base + msc->index * 0x100;
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msc->msu_base = base;
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err = intel_th_msu_init(msc);
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if (err)
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return err;
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err = intel_th_msc_init(msc);
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if (err)
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@ -1520,6 +1580,7 @@ static void intel_th_msc_remove(struct intel_th_device *thdev)
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int ret;
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intel_th_msc_deactivate(thdev);
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intel_th_msu_deinit(msc);
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/*
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* Buffers should not be used at this point except if the
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@ -1533,6 +1594,7 @@ static void intel_th_msc_remove(struct intel_th_device *thdev)
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static struct intel_th_driver intel_th_msc_driver = {
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.probe = intel_th_msc_probe,
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.remove = intel_th_msc_remove,
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.irq = intel_th_msc_interrupt,
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.activate = intel_th_msc_activate,
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.deactivate = intel_th_msc_deactivate,
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.fops = &intel_th_msc_fops,
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@ -11,6 +11,7 @@
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enum {
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REG_MSU_MSUPARAMS = 0x0000,
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REG_MSU_MSUSTS = 0x0008,
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REG_MSU_MINTCTL = 0x0004, /* MSU-global interrupt control */
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REG_MSU_MSC0CTL = 0x0100, /* MSC0 control */
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REG_MSU_MSC0STS = 0x0104, /* MSC0 status */
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REG_MSU_MSC0BAR = 0x0108, /* MSC0 output base address */
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@ -28,6 +29,8 @@ enum {
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/* MSUSTS bits */
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#define MSUSTS_MSU_INT BIT(0)
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#define MSUSTS_MSC0BLAST BIT(16)
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#define MSUSTS_MSC1BLAST BIT(24)
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/* MSCnCTL bits */
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#define MSC_EN BIT(0)
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@ -36,6 +39,11 @@ enum {
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#define MSC_MODE (BIT(4) | BIT(5))
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#define MSC_LEN (BIT(8) | BIT(9) | BIT(10))
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/* MINTCTL bits */
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#define MICDE BIT(0)
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#define M0BLIE BIT(16)
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#define M1BLIE BIT(24)
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/* MSC operating modes (MSC_MODE) */
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enum {
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MSC_MODE_SINGLE = 0,
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