powerpc/p4080: Add basic support for p4080ds platform
Add basic support for the P4080 DS reference board. None of the data path devices (ethernet, crypto, pme) are support at this time. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
3bc265627a
commit
ab2f489294
554
arch/powerpc/boot/dts/p4080ds.dts
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554
arch/powerpc/boot/dts/p4080ds.dts
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/*
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* P4080DS Device Tree Source
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*
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* Copyright 2009 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "fsl,P4080DS";
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compatible = "fsl,P4080DS";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ccsr = &soc;
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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serial3 = &serial3;
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pci0 = &pci0;
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pci1 = &pci1;
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pci2 = &pci2;
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usb0 = &usb0;
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usb1 = &usb1;
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dma0 = &dma0;
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dma1 = &dma1;
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sdhc = &sdhc;
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rio0 = &rapidio0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: PowerPC,4080@0 {
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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};
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};
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cpu1: PowerPC,4080@1 {
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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};
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};
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cpu2: PowerPC,4080@2 {
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device_type = "cpu";
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reg = <2>;
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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};
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};
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cpu3: PowerPC,4080@3 {
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device_type = "cpu";
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reg = <3>;
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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};
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};
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cpu4: PowerPC,4080@4 {
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device_type = "cpu";
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reg = <4>;
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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};
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};
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cpu5: PowerPC,4080@5 {
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device_type = "cpu";
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reg = <5>;
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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};
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};
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cpu6: PowerPC,4080@6 {
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device_type = "cpu";
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reg = <6>;
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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};
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};
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cpu7: PowerPC,4080@7 {
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device_type = "cpu";
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reg = <7>;
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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};
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};
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};
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memory {
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device_type = "memory";
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};
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soc: soc@ffe000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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corenet-law@0 {
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compatible = "fsl,corenet-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <32>;
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};
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memory-controller@8000 {
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compatible = "fsl,p4080-memory-controller";
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reg = <0x8000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <0x12 2>;
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};
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memory-controller@9000 {
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compatible = "fsl,p4080-memory-controller";
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reg = <0x9000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <0x12 2>;
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};
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corenet-cf@18000 {
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compatible = "fsl,corenet-cf";
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reg = <0x18000 0x1000>;
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fsl,ccf-num-csdids = <32>;
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fsl,ccf-num-snoopids = <32>;
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};
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iommu@20000 {
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compatible = "fsl,p4080-pamu";
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reg = <0x20000 0x10000>;
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interrupts = <24 2>;
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interrupt-parent = <&mpic>;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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dma0: dma@100300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
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reg = <0x100300 0x4>;
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ranges = <0x0 0x100100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <28 2>;
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};
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dma-channel@80 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <29 2>;
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};
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dma-channel@100 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <30 2>;
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};
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dma-channel@180 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <31 2>;
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};
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};
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dma1: dma@101300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
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reg = <0x101300 0x4>;
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ranges = <0x0 0x101100 0x200>;
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cell-index = <1>;
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dma-channel@0 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <32 2>;
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};
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dma-channel@80 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <33 2>;
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};
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dma-channel@100 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <34 2>;
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};
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dma-channel@180 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <35 2>;
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};
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};
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spi@110000 {
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cell-index = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,espi";
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reg = <0x110000 0x1000>;
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interrupts = <53 0x2>;
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interrupt-parent = <&mpic>;
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espi,num-ss-bits = <4>;
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mode = "cpu";
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fsl_m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,espi-flash";
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reg = <0>;
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linux,modalias = "fsl_m25p80";
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spi-max-frequency = <40000000>; /* input clock */
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partition@u-boot {
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label = "u-boot";
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reg = <0x00000000 0x00100000>;
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read-only;
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};
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partition@kernel {
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label = "kernel";
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reg = <0x00100000 0x00500000>;
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read-only;
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};
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partition@dtb {
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label = "dtb";
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reg = <0x00600000 0x00100000>;
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read-only;
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};
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partition@fs {
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label = "file system";
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reg = <0x00700000 0x00900000>;
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};
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};
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};
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sdhc: sdhc@114000 {
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compatible = "fsl,p4080-esdhc", "fsl,esdhc";
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reg = <0x114000 0x1000>;
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interrupts = <48 2>;
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interrupt-parent = <&mpic>;
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};
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i2c@118000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x118000 0x100>;
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interrupts = <38 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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i2c@118100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x118100 0x100>;
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interrupts = <38 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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eeprom@51 {
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compatible = "at24,24c256";
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reg = <0x51>;
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};
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eeprom@52 {
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compatible = "at24,24c256";
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reg = <0x52>;
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};
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rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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interrupts = <0 0x1>;
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interrupt-parent = <&mpic>;
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};
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};
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i2c@119000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <2>;
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compatible = "fsl-i2c";
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reg = <0x119000 0x100>;
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interrupts = <39 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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i2c@119100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <3>;
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compatible = "fsl-i2c";
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reg = <0x119100 0x100>;
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interrupts = <39 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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serial0: serial@11c500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x11c500 0x100>;
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clock-frequency = <0>;
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interrupts = <36 2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@11c600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x11c600 0x100>;
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clock-frequency = <0>;
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interrupts = <36 2>;
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interrupt-parent = <&mpic>;
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};
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serial2: serial@11d500 {
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cell-index = <2>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x11d500 0x100>;
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clock-frequency = <0>;
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interrupts = <37 2>;
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interrupt-parent = <&mpic>;
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};
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serial3: serial@11d600 {
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cell-index = <3>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x11d600 0x100>;
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clock-frequency = <0>;
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interrupts = <37 2>;
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interrupt-parent = <&mpic>;
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};
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gpio0: gpio@130000 {
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compatible = "fsl,p4080-gpio";
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reg = <0x130000 0x1000>;
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interrupts = <55 2>;
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interrupt-parent = <&mpic>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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usb0: usb@210000 {
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compatible = "fsl,p4080-usb2-mph",
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"fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
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reg = <0x210000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <44 0x2>;
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phy_type = "ulpi";
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};
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usb1: usb@211000 {
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compatible = "fsl,p4080-usb2-dr",
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"fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
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reg = <0x211000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <45 0x2>;
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dr_mode = "host";
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phy_type = "ulpi";
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};
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};
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rapidio0: rapidio@ffe0c0000 {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "fsl,rapidio-delta";
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reg = <0xf 0xfe0c0000 0 0x20000>;
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ranges = <0 0 0xf 0xf5000000 0 0x01000000>;
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interrupt-parent = <&mpic>;
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/* err_irq bell_outb_irq bell_inb_irq
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msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
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interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
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};
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localbus@ffe124000 {
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compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
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reg = <0xf 0xfe124000 0 0x1000>;
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interrupts = <25 2>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0xf 0xe8000000 0x08000000>;
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x08000000>;
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bank-width = <2>;
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device-width = <2>;
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};
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};
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pci0: pcie@ffe200000 {
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compatible = "fsl,p4080-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xf 0xfe200000 0 0x1000>;
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bus-range = <0x0 0xff>;
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ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
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0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
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clock-frequency = <0x1fca055>;
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 40 1
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0000 0 0 2 &mpic 1 1
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0000 0 0 3 &mpic 2 1
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0000 0 0 4 &mpic 3 1
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>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x20000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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pci1: pcie@ffe201000 {
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compatible = "fsl,p4080-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xf 0xfe201000 0 0x1000>;
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bus-range = <0 0xff>;
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ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
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0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
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clock-frequency = <0x1fca055>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 41 1
|
||||
0000 0 0 2 &mpic 5 1
|
||||
0000 0 0 3 &mpic 6 1
|
||||
0000 0 0 4 &mpic 7 1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci2: pcie@ffe202000 {
|
||||
compatible = "fsl,p4080-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xf 0xfe202000 0 0x1000>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 42 1
|
||||
0000 0 0 2 &mpic 9 1
|
||||
0000 0 0 3 &mpic 10 1
|
||||
0000 0 0 4 &mpic 11 1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -145,6 +145,18 @@ config SBC8560
|
|||
help
|
||||
This option enables support for the Wind River SBC8560 board
|
||||
|
||||
config P4080_DS
|
||||
bool "Freescale P4080 DS"
|
||||
select DEFAULT_UIMAGE
|
||||
select PPC_FSL_BOOK3E
|
||||
select PPC_E500MC
|
||||
select PHYS_64BIT
|
||||
select SWIOTLB
|
||||
select MPC8xxx_GPIO
|
||||
select HAS_RAPIDIO
|
||||
help
|
||||
This option enables support for the P4080 DS board
|
||||
|
||||
endif # FSL_SOC_BOOKE
|
||||
|
||||
config TQM85xx
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.o
|
|||
obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
|
||||
obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
|
||||
obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
|
||||
obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
|
||||
obj-$(CONFIG_STX_GP3) += stx_gp3.o
|
||||
obj-$(CONFIG_TQM85xx) += tqm85xx.o
|
||||
obj-$(CONFIG_SBC8560) += sbc8560.o
|
||||
|
|
|
|||
125
arch/powerpc/platforms/85xx/corenet_ds.c
Normal file
125
arch/powerpc/platforms/85xx/corenet_ds.c
Normal file
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* Corenet based SoC DS Setup
|
||||
*
|
||||
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
|
||||
*
|
||||
* Copyright 2009 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/lmb.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
|
||||
void __init corenet_ds_pic_init(void)
|
||||
{
|
||||
struct mpic *mpic;
|
||||
struct resource r;
|
||||
struct device_node *np = NULL;
|
||||
unsigned int flags = MPIC_PRIMARY | MPIC_BIG_ENDIAN |
|
||||
MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU;
|
||||
|
||||
np = of_find_node_by_type(np, "open-pic");
|
||||
|
||||
if (np == NULL) {
|
||||
printk(KERN_ERR "Could not find open-pic node\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (of_address_to_resource(np, 0, &r)) {
|
||||
printk(KERN_ERR "Failed to map mpic register space\n");
|
||||
of_node_put(np);
|
||||
return;
|
||||
}
|
||||
|
||||
if (ppc_md.get_irq == mpic_get_coreint_irq)
|
||||
flags |= MPIC_ENABLE_COREINT;
|
||||
|
||||
mpic = mpic_alloc(np, r.start, flags, 0, 256, " OpenPIC ");
|
||||
BUG_ON(mpic == NULL);
|
||||
|
||||
mpic_init(mpic);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static int primary_phb_addr;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Setup the architecture
|
||||
*/
|
||||
#ifdef CONFIG_SMP
|
||||
void __init mpc85xx_smp_init(void);
|
||||
#endif
|
||||
|
||||
void __init corenet_ds_setup_arch(void)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
struct device_node *np;
|
||||
struct pci_controller *hose;
|
||||
#endif
|
||||
dma_addr_t max = 0xffffffff;
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
mpc85xx_smp_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
for_each_compatible_node(np, "pci", "fsl,p4080-pcie") {
|
||||
struct resource rsrc;
|
||||
of_address_to_resource(np, 0, &rsrc);
|
||||
if ((rsrc.start & 0xfffff) == primary_phb_addr)
|
||||
fsl_add_bridge(np, 1);
|
||||
else
|
||||
fsl_add_bridge(np, 0);
|
||||
|
||||
hose = pci_find_hose_for_OF_device(np);
|
||||
max = min(max, hose->dma_window_base_cur +
|
||||
hose->dma_window_size);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
if (lmb_end_of_DRAM() > max) {
|
||||
ppc_swiotlb_enable = 1;
|
||||
set_pci_dma_ops(&swiotlb_dma_ops);
|
||||
ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
|
||||
}
|
||||
#endif
|
||||
pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_device_ids[] __devinitconst = {
|
||||
{
|
||||
.compatible = "simple-bus"
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,rapidio-delta",
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
int __init corenet_ds_publish_devices(void)
|
||||
{
|
||||
return of_platform_bus_probe(NULL, of_device_ids, NULL);
|
||||
}
|
||||
19
arch/powerpc/platforms/85xx/corenet_ds.h
Normal file
19
arch/powerpc/platforms/85xx/corenet_ds.h
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Corenet based SoC DS Setup
|
||||
*
|
||||
* Copyright 2009 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef CORENET_DS_H
|
||||
#define CORENET_DS_H
|
||||
|
||||
extern void __init corenet_ds_pic_init(void);
|
||||
extern void __init corenet_ds_setup_arch(void);
|
||||
extern int __init corenet_ds_publish_devices(void);
|
||||
|
||||
#endif
|
||||
74
arch/powerpc/platforms/85xx/p4080_ds.c
Normal file
74
arch/powerpc/platforms/85xx/p4080_ds.c
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* P4080 DS Setup
|
||||
*
|
||||
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
|
||||
*
|
||||
* Copyright 2009 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
|
||||
#include "corenet_ds.h"
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static int primary_phb_addr;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*/
|
||||
static int __init p4080_ds_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "fsl,P4080DS")) {
|
||||
#ifdef CONFIG_PCI
|
||||
/* treat PCIe1 as primary,
|
||||
* shouldn't matter as we have no ISA on the board
|
||||
*/
|
||||
primary_phb_addr = 0x0000;
|
||||
#endif
|
||||
return 1;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
define_machine(p4080_ds) {
|
||||
.name = "P4080 DS",
|
||||
.probe = p4080_ds_probe,
|
||||
.setup_arch = corenet_ds_setup_arch,
|
||||
.init_IRQ = corenet_ds_pic_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
.get_irq = mpic_get_coreint_irq,
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
};
|
||||
|
||||
machine_device_initcall(p4080_ds, corenet_ds_publish_devices);
|
||||
machine_arch_initcall(p4080_ds, swiotlb_setup_bus_notifier);
|
||||
Loading…
Reference in a new issue