PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller
Add PCIe Root Port driver for Xilinx PCIe NWL bridge IP. [bhelgaas: wait for link like dw_pcie_wait_for_link(), simplify bitmap error path, typos, whitespace, fold in Dan Carpenter's PTR_ERR() fix] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Rob Herring <robh@kernel.org>hifive-unleashed-5.1
Bharat Kumar Gogada
Bjorn Helgaas
parent
92e963f50f
commit
ab597d35ef
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@ -0,0 +1,68 @@
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* Xilinx NWL PCIe Root Port Bridge DT description
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Required properties:
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- compatible: Should contain "xlnx,nwl-pcie-2.11"
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- #address-cells: Address representation for root ports, set to <3>
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- #size-cells: Size representation for root ports, set to <2>
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- reg: Should contain Bridge, PCIe Controller registers location,
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configuration space, and length
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- reg-names: Must include the following entries:
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"breg": bridge registers
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"pcireg": PCIe controller registers
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"cfg": configuration space region
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- device_type: must be "pci"
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- interrupts: Should contain NWL PCIe interrupt
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- interrupt-names: Must include the following entries:
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"msi1, msi0": interrupt asserted when MSI is received
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"intx": interrupt asserted when a legacy interrupt is received
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"misc": interrupt asserted when miscellaneous is received
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- interrupt-map-mask and interrupt-map: standard PCI properties to define the
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mapping of the PCI interface to interrupt numbers.
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- ranges: ranges for the PCI memory regions (I/O space region is not
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supported by hardware)
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Please refer to the standard PCI bus binding document for a more
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detailed explanation
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- msi-controller: indicates that this is MSI controller node
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- msi-parent: MSI parent of the root complex itself
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- legacy-interrupt-controller: Interrupt controller device node for Legacy interrupts
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: should be set to 1
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- #address-cells: specifies the number of cells needed to encode an
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address. The value must be 0.
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Example:
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++++++++
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nwl_pcie: pcie@fd0e0000 {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "xlnx,nwl-pcie-2.11";
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#interrupt-cells = <1>;
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msi-controller;
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device_type = "pci";
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interrupt-parent = <&gic>;
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interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>;
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interrupt-names = "msi0", "msi1", "intx", "dummy", "misc";
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
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<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
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<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
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<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
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msi-parent = <&nwl_pcie>;
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reg = <0x0 0xfd0e0000 0x0 0x1000>,
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<0x0 0xfd480000 0x0 0x1000>,
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<0x0 0xe0000000 0x0 0x1000000>;
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reg-names = "breg", "pcireg", "cfg";
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ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
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pcie_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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@ -16,6 +16,16 @@ config PCI_MVEBU
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depends on ARCH_MVEBU || ARCH_DOVE
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depends on OF
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config PCIE_XILINX_NWL
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bool "NWL PCIe Core"
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depends on ARCH_ZYNQMP
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select PCI_MSI_IRQ_DOMAIN if PCI_MSI
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help
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Say 'Y' here if you want kernel support for Xilinx
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NWL PCIe controller. The controller can act as Root Port
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or End Point. The current option selection will only
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support root port enabling.
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config PCIE_DW
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bool
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@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
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obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
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obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
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obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
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obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
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obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
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obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o
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obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
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@ -0,0 +1,881 @@
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/*
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* PCIe host controller driver for NWL PCIe Bridge
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* Based on pcie-xilinx.c, pci-tegra.c
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*
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* (C) Copyright 2014 - 2015, Xilinx, Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/irqchip/chained_irq.h>
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/* Bridge core config registers */
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#define BRCFG_PCIE_RX0 0x00000000
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#define BRCFG_INTERRUPT 0x00000010
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#define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
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/* Egress - Bridge translation registers */
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#define E_BREG_CAPABILITIES 0x00000200
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#define E_BREG_CONTROL 0x00000208
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#define E_BREG_BASE_LO 0x00000210
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#define E_BREG_BASE_HI 0x00000214
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#define E_ECAM_CAPABILITIES 0x00000220
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#define E_ECAM_CONTROL 0x00000228
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#define E_ECAM_BASE_LO 0x00000230
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#define E_ECAM_BASE_HI 0x00000234
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/* Ingress - address translations */
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#define I_MSII_CAPABILITIES 0x00000300
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#define I_MSII_CONTROL 0x00000308
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#define I_MSII_BASE_LO 0x00000310
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#define I_MSII_BASE_HI 0x00000314
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#define I_ISUB_CONTROL 0x000003E8
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#define SET_ISUB_CONTROL BIT(0)
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/* Rxed msg fifo - Interrupt status registers */
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#define MSGF_MISC_STATUS 0x00000400
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#define MSGF_MISC_MASK 0x00000404
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#define MSGF_LEG_STATUS 0x00000420
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#define MSGF_LEG_MASK 0x00000424
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#define MSGF_MSI_STATUS_LO 0x00000440
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#define MSGF_MSI_STATUS_HI 0x00000444
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#define MSGF_MSI_MASK_LO 0x00000448
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#define MSGF_MSI_MASK_HI 0x0000044C
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/* Msg filter mask bits */
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#define CFG_ENABLE_PM_MSG_FWD BIT(1)
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#define CFG_ENABLE_INT_MSG_FWD BIT(2)
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#define CFG_ENABLE_ERR_MSG_FWD BIT(3)
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#define CFG_ENABLE_SLT_MSG_FWD BIT(5)
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#define CFG_ENABLE_VEN_MSG_FWD BIT(7)
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#define CFG_ENABLE_OTH_MSG_FWD BIT(13)
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#define CFG_ENABLE_VEN_MSG_EN BIT(14)
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#define CFG_ENABLE_VEN_MSG_VEN_INV BIT(15)
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#define CFG_ENABLE_VEN_MSG_VEN_ID GENMASK(31, 16)
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#define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
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CFG_ENABLE_INT_MSG_FWD | \
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CFG_ENABLE_ERR_MSG_FWD | \
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CFG_ENABLE_SLT_MSG_FWD | \
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CFG_ENABLE_VEN_MSG_FWD | \
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CFG_ENABLE_OTH_MSG_FWD | \
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CFG_ENABLE_VEN_MSG_EN | \
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CFG_ENABLE_VEN_MSG_VEN_INV | \
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CFG_ENABLE_VEN_MSG_VEN_ID)
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/* Misc interrupt status mask bits */
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#define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
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#define MSGF_MISC_SR_RXMSG_OVER BIT(1)
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#define MSGF_MISC_SR_SLAVE_ERR BIT(4)
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#define MSGF_MISC_SR_MASTER_ERR BIT(5)
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#define MSGF_MISC_SR_I_ADDR_ERR BIT(6)
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#define MSGF_MISC_SR_E_ADDR_ERR BIT(7)
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#define MSGF_MISC_SR_UR_DETECT BIT(20)
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#define MSGF_MISC_SR_PCIE_CORE GENMASK(18, 16)
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#define MSGF_MISC_SR_PCIE_CORE_ERR GENMASK(31, 22)
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#define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
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MSGF_MISC_SR_RXMSG_OVER | \
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MSGF_MISC_SR_SLAVE_ERR | \
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MSGF_MISC_SR_MASTER_ERR | \
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MSGF_MISC_SR_I_ADDR_ERR | \
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MSGF_MISC_SR_E_ADDR_ERR | \
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MSGF_MISC_SR_UR_DETECT | \
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MSGF_MISC_SR_PCIE_CORE | \
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MSGF_MISC_SR_PCIE_CORE_ERR)
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/* Legacy interrupt status mask bits */
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#define MSGF_LEG_SR_INTA BIT(0)
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#define MSGF_LEG_SR_INTB BIT(1)
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#define MSGF_LEG_SR_INTC BIT(2)
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#define MSGF_LEG_SR_INTD BIT(3)
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#define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
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MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
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/* MSI interrupt status mask bits */
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#define MSGF_MSI_SR_LO_MASK BIT(0)
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#define MSGF_MSI_SR_HI_MASK BIT(0)
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#define MSII_PRESENT BIT(0)
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#define MSII_ENABLE BIT(0)
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#define MSII_STATUS_ENABLE BIT(15)
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/* Bridge config interrupt mask */
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#define BRCFG_INTERRUPT_MASK BIT(0)
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#define BREG_PRESENT BIT(0)
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#define BREG_ENABLE BIT(0)
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#define BREG_ENABLE_FORCE BIT(1)
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/* E_ECAM status mask bits */
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#define E_ECAM_PRESENT BIT(0)
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#define E_ECAM_CR_ENABLE BIT(0)
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#define E_ECAM_SIZE_LOC GENMASK(20, 16)
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#define E_ECAM_SIZE_SHIFT 16
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#define ECAM_BUS_LOC_SHIFT 20
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#define ECAM_DEV_LOC_SHIFT 12
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#define NWL_ECAM_VALUE_DEFAULT 12
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#define CFG_DMA_REG_BAR GENMASK(2, 0)
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#define INT_PCI_MSI_NR (2 * 32)
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#define INTX_NUM 4
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/* Readin the PS_LINKUP */
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#define PS_LINKUP_OFFSET 0x00000238
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#define PCIE_PHY_LINKUP_BIT BIT(0)
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#define PHY_RDY_LINKUP_BIT BIT(1)
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/* Parameters for the waiting for link up routine */
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#define LINK_WAIT_MAX_RETRIES 10
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#define LINK_WAIT_USLEEP_MIN 90000
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#define LINK_WAIT_USLEEP_MAX 100000
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struct nwl_msi { /* MSI information */
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struct irq_domain *msi_domain;
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unsigned long *bitmap;
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struct irq_domain *dev_domain;
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struct mutex lock; /* protect bitmap variable */
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int irq_msi0;
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int irq_msi1;
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};
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struct nwl_pcie {
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struct device *dev;
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void __iomem *breg_base;
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void __iomem *pcireg_base;
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void __iomem *ecam_base;
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phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
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phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
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phys_addr_t phys_ecam_base; /* Physical Configuration Base */
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u32 breg_size;
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u32 pcie_reg_size;
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u32 ecam_size;
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int irq_intx;
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int irq_misc;
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u32 ecam_value;
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u8 last_busno;
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u8 root_busno;
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struct nwl_msi msi;
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struct irq_domain *legacy_irq_domain;
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};
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static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
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{
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return readl(pcie->breg_base + off);
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}
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static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
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{
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writel(val, pcie->breg_base + off);
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}
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static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
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{
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if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
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return true;
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return false;
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}
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static bool nwl_phy_link_up(struct nwl_pcie *pcie)
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{
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if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
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return true;
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return false;
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}
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static int nwl_wait_for_link(struct nwl_pcie *pcie)
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{
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int retries;
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/* check if the link is up or not */
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for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
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if (nwl_phy_link_up(pcie))
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return 0;
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usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
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}
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dev_err(pcie->dev, "PHY link never came up\n");
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return -ETIMEDOUT;
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}
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static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
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{
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struct nwl_pcie *pcie = bus->sysdata;
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/* Check link before accessing downstream ports */
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if (bus->number != pcie->root_busno) {
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if (!nwl_pcie_link_up(pcie))
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return false;
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}
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/* Only one device down on each root port */
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if (bus->number == pcie->root_busno && devfn > 0)
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return false;
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return true;
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}
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/**
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* nwl_pcie_map_bus - Get configuration base
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*
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* @bus: Bus structure of current bus
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* @devfn: Device/function
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* @where: Offset from base
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*
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* Return: Base address of the configuration space needed to be
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* accessed.
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*/
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static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
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int where)
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{
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struct nwl_pcie *pcie = bus->sysdata;
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int relbus;
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if (!nwl_pcie_valid_device(bus, devfn))
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return NULL;
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relbus = (bus->number << ECAM_BUS_LOC_SHIFT) |
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(devfn << ECAM_DEV_LOC_SHIFT);
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return pcie->ecam_base + relbus + where;
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}
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/* PCIe operations */
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static struct pci_ops nwl_pcie_ops = {
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.map_bus = nwl_pcie_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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};
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static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
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{
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struct nwl_pcie *pcie = data;
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u32 misc_stat;
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/* Checking for misc interrupts */
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misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
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MSGF_MISC_SR_MASKALL;
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if (!misc_stat)
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return IRQ_NONE;
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if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
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dev_err(pcie->dev, "Received Message FIFO Overflow\n");
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if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
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dev_err(pcie->dev, "Slave error\n");
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if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
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dev_err(pcie->dev, "Master error\n");
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if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
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dev_err(pcie->dev,
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"In Misc Ingress address translation error\n");
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if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
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dev_err(pcie->dev,
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"In Misc Egress address translation error\n");
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if (misc_stat & MSGF_MISC_SR_PCIE_CORE_ERR)
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dev_err(pcie->dev, "PCIe Core error\n");
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/* Clear misc interrupt status */
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nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
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return IRQ_HANDLED;
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}
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static void nwl_pcie_leg_handler(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct nwl_pcie *pcie;
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unsigned long status;
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u32 bit;
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u32 virq;
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chained_irq_enter(chip, desc);
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pcie = irq_desc_get_handler_data(desc);
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while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
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MSGF_LEG_SR_MASKALL) != 0) {
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for_each_set_bit(bit, &status, INTX_NUM) {
|
||||
virq = irq_find_mapping(pcie->legacy_irq_domain,
|
||||
bit + 1);
|
||||
if (virq)
|
||||
generic_handle_irq(virq);
|
||||
}
|
||||
}
|
||||
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
|
||||
{
|
||||
struct nwl_msi *msi;
|
||||
unsigned long status;
|
||||
u32 bit;
|
||||
u32 virq;
|
||||
|
||||
msi = &pcie->msi;
|
||||
|
||||
while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
|
||||
for_each_set_bit(bit, &status, 32) {
|
||||
nwl_bridge_writel(pcie, 1 << bit, status_reg);
|
||||
virq = irq_find_mapping(msi->dev_domain, bit);
|
||||
if (virq)
|
||||
generic_handle_irq(virq);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
|
||||
irq_hw_number_t hwirq)
|
||||
{
|
||||
irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
|
||||
irq_set_chip_data(irq, domain->host_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops legacy_domain_ops = {
|
||||
.map = nwl_legacy_map,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PCI_MSI
|
||||
static struct irq_chip nwl_msi_irq_chip = {
|
||||
.name = "nwl_pcie:msi",
|
||||
.irq_enable = unmask_msi_irq,
|
||||
.irq_disable = mask_msi_irq,
|
||||
.irq_mask = mask_msi_irq,
|
||||
.irq_unmask = unmask_msi_irq,
|
||||
|
||||
};
|
||||
|
||||
static struct msi_domain_info nwl_msi_domain_info = {
|
||||
.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
|
||||
MSI_FLAG_MULTI_PCI_MSI),
|
||||
.chip = &nwl_msi_irq_chip,
|
||||
};
|
||||
#endif
|
||||
|
||||
static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
|
||||
{
|
||||
struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
|
||||
phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
|
||||
|
||||
msg->address_lo = lower_32_bits(msi_addr);
|
||||
msg->address_hi = upper_32_bits(msi_addr);
|
||||
msg->data = data->hwirq;
|
||||
}
|
||||
|
||||
static int nwl_msi_set_affinity(struct irq_data *irq_data,
|
||||
const struct cpumask *mask, bool force)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static struct irq_chip nwl_irq_chip = {
|
||||
.name = "Xilinx MSI",
|
||||
.irq_compose_msi_msg = nwl_compose_msi_msg,
|
||||
.irq_set_affinity = nwl_msi_set_affinity,
|
||||
};
|
||||
|
||||
static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
|
||||
unsigned int nr_irqs, void *args)
|
||||
{
|
||||
struct nwl_pcie *pcie = domain->host_data;
|
||||
struct nwl_msi *msi = &pcie->msi;
|
||||
int bit;
|
||||
int i;
|
||||
|
||||
mutex_lock(&msi->lock);
|
||||
bit = bitmap_find_next_zero_area(msi->bitmap, INT_PCI_MSI_NR, 0,
|
||||
nr_irqs, 0);
|
||||
if (bit >= INT_PCI_MSI_NR) {
|
||||
mutex_unlock(&msi->lock);
|
||||
return -ENOSPC;
|
||||
}
|
||||
|
||||
bitmap_set(msi->bitmap, bit, nr_irqs);
|
||||
|
||||
for (i = 0; i < nr_irqs; i++) {
|
||||
irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
|
||||
domain->host_data, handle_simple_irq,
|
||||
NULL, NULL);
|
||||
}
|
||||
mutex_unlock(&msi->lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
|
||||
unsigned int nr_irqs)
|
||||
{
|
||||
struct irq_data *data = irq_domain_get_irq_data(domain, virq);
|
||||
struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
|
||||
struct nwl_msi *msi = &pcie->msi;
|
||||
|
||||
mutex_lock(&msi->lock);
|
||||
bitmap_clear(msi->bitmap, data->hwirq, nr_irqs);
|
||||
mutex_unlock(&msi->lock);
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops dev_msi_domain_ops = {
|
||||
.alloc = nwl_irq_domain_alloc,
|
||||
.free = nwl_irq_domain_free,
|
||||
};
|
||||
|
||||
static void nwl_msi_free_irq_domain(struct nwl_pcie *pcie)
|
||||
{
|
||||
struct nwl_msi *msi = &pcie->msi;
|
||||
|
||||
if (msi->irq_msi0)
|
||||
irq_set_chained_handler_and_data(msi->irq_msi0, NULL, NULL);
|
||||
if (msi->irq_msi1)
|
||||
irq_set_chained_handler_and_data(msi->irq_msi1, NULL, NULL);
|
||||
|
||||
if (msi->msi_domain)
|
||||
irq_domain_remove(msi->msi_domain);
|
||||
if (msi->dev_domain)
|
||||
irq_domain_remove(msi->dev_domain);
|
||||
|
||||
kfree(msi->bitmap);
|
||||
msi->bitmap = NULL;
|
||||
}
|
||||
|
||||
static void nwl_pcie_free_irq_domain(struct nwl_pcie *pcie)
|
||||
{
|
||||
int i;
|
||||
u32 irq;
|
||||
|
||||
for (i = 0; i < INTX_NUM; i++) {
|
||||
irq = irq_find_mapping(pcie->legacy_irq_domain, i + 1);
|
||||
if (irq > 0)
|
||||
irq_dispose_mapping(irq);
|
||||
}
|
||||
if (pcie->legacy_irq_domain)
|
||||
irq_domain_remove(pcie->legacy_irq_domain);
|
||||
|
||||
nwl_msi_free_irq_domain(pcie);
|
||||
}
|
||||
|
||||
static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
|
||||
{
|
||||
#ifdef CONFIG_PCI_MSI
|
||||
struct fwnode_handle *fwnode = of_node_to_fwnode(pcie->dev->of_node);
|
||||
struct nwl_msi *msi = &pcie->msi;
|
||||
|
||||
msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
|
||||
&dev_msi_domain_ops, pcie);
|
||||
if (!msi->dev_domain) {
|
||||
dev_err(pcie->dev, "failed to create dev IRQ domain\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
msi->msi_domain = pci_msi_create_irq_domain(fwnode,
|
||||
&nwl_msi_domain_info,
|
||||
msi->dev_domain);
|
||||
if (!msi->msi_domain) {
|
||||
dev_err(pcie->dev, "failed to create msi IRQ domain\n");
|
||||
irq_domain_remove(msi->dev_domain);
|
||||
return -ENOMEM;
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
|
||||
{
|
||||
struct device_node *node = pcie->dev->of_node;
|
||||
struct device_node *legacy_intc_node;
|
||||
|
||||
legacy_intc_node = of_get_next_child(node, NULL);
|
||||
if (!legacy_intc_node) {
|
||||
dev_err(pcie->dev, "No legacy intc node found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
|
||||
INTX_NUM,
|
||||
&legacy_domain_ops,
|
||||
pcie);
|
||||
|
||||
if (!pcie->legacy_irq_domain) {
|
||||
dev_err(pcie->dev, "failed to create IRQ domain\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
nwl_pcie_init_msi_irq_domain(pcie);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nwl_pcie_enable_msi(struct nwl_pcie *pcie, struct pci_bus *bus)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(pcie->dev);
|
||||
struct nwl_msi *msi = &pcie->msi;
|
||||
unsigned long base;
|
||||
int ret;
|
||||
int size = BITS_TO_LONGS(INT_PCI_MSI_NR) * sizeof(long);
|
||||
|
||||
mutex_init(&msi->lock);
|
||||
|
||||
msi->bitmap = kzalloc(size, GFP_KERNEL);
|
||||
if (!msi->bitmap)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Get msi_1 IRQ number */
|
||||
msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
|
||||
if (msi->irq_msi1 < 0) {
|
||||
dev_err(&pdev->dev, "failed to get IRQ#%d\n", msi->irq_msi1);
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
irq_set_chained_handler_and_data(msi->irq_msi1,
|
||||
nwl_pcie_msi_handler_high, pcie);
|
||||
|
||||
/* Get msi_0 IRQ number */
|
||||
msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
|
||||
if (msi->irq_msi0 < 0) {
|
||||
dev_err(&pdev->dev, "failed to get IRQ#%d\n", msi->irq_msi0);
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
irq_set_chained_handler_and_data(msi->irq_msi0,
|
||||
nwl_pcie_msi_handler_low, pcie);
|
||||
|
||||
/* Check for msii_present bit */
|
||||
ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
|
||||
if (!ret) {
|
||||
dev_err(pcie->dev, "MSI not present\n");
|
||||
ret = -EIO;
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Enable MSII */
|
||||
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
|
||||
MSII_ENABLE, I_MSII_CONTROL);
|
||||
|
||||
/* Enable MSII status */
|
||||
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
|
||||
MSII_STATUS_ENABLE, I_MSII_CONTROL);
|
||||
|
||||
/* setup AFI/FPCI range */
|
||||
base = pcie->phys_pcie_reg_base;
|
||||
nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
|
||||
nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
|
||||
|
||||
/*
|
||||
* For high range MSI interrupts: disable, clear any pending,
|
||||
* and enable
|
||||
*/
|
||||
nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
|
||||
|
||||
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
|
||||
MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
|
||||
|
||||
nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
|
||||
|
||||
/*
|
||||
* For low range MSI interrupts: disable, clear any pending,
|
||||
* and enable
|
||||
*/
|
||||
nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
|
||||
|
||||
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
|
||||
MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
|
||||
|
||||
nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
|
||||
|
||||
return 0;
|
||||
err:
|
||||
kfree(msi->bitmap);
|
||||
msi->bitmap = NULL;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(pcie->dev);
|
||||
u32 breg_val, ecam_val, first_busno = 0;
|
||||
int err;
|
||||
|
||||
breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
|
||||
if (!breg_val) {
|
||||
dev_err(pcie->dev, "BREG is not present\n");
|
||||
return breg_val;
|
||||
}
|
||||
|
||||
/* Write bridge_off to breg base */
|
||||
nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
|
||||
E_BREG_BASE_LO);
|
||||
nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
|
||||
E_BREG_BASE_HI);
|
||||
|
||||
/* Enable BREG */
|
||||
nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
|
||||
E_BREG_CONTROL);
|
||||
|
||||
/* Disable DMA channel registers */
|
||||
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
|
||||
CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
|
||||
|
||||
/* Enable Ingress subtractive decode translation */
|
||||
nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
|
||||
|
||||
/* Enable msg filtering details */
|
||||
nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
|
||||
BRCFG_PCIE_RX_MSG_FILTER);
|
||||
|
||||
err = nwl_wait_for_link(pcie);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
|
||||
if (!ecam_val) {
|
||||
dev_err(pcie->dev, "ECAM is not present\n");
|
||||
return ecam_val;
|
||||
}
|
||||
|
||||
/* Enable ECAM */
|
||||
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
|
||||
E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
|
||||
|
||||
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
|
||||
(pcie->ecam_value << E_ECAM_SIZE_SHIFT),
|
||||
E_ECAM_CONTROL);
|
||||
|
||||
nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
|
||||
E_ECAM_BASE_LO);
|
||||
nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
|
||||
E_ECAM_BASE_HI);
|
||||
|
||||
/* Get bus range */
|
||||
ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
|
||||
pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
|
||||
/* Write primary, secondary and subordinate bus numbers */
|
||||
ecam_val = first_busno;
|
||||
ecam_val |= (first_busno + 1) << 8;
|
||||
ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
|
||||
writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
|
||||
|
||||
if (nwl_pcie_link_up(pcie))
|
||||
dev_info(pcie->dev, "Link is UP\n");
|
||||
else
|
||||
dev_info(pcie->dev, "Link is DOWN\n");
|
||||
|
||||
/* Get misc IRQ number */
|
||||
pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
|
||||
if (pcie->irq_misc < 0) {
|
||||
dev_err(&pdev->dev, "failed to get misc IRQ %d\n",
|
||||
pcie->irq_misc);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
err = devm_request_irq(pcie->dev, pcie->irq_misc,
|
||||
nwl_pcie_misc_handler, IRQF_SHARED,
|
||||
"nwl_pcie:misc", pcie);
|
||||
if (err) {
|
||||
dev_err(pcie->dev, "fail to register misc IRQ#%d\n",
|
||||
pcie->irq_misc);
|
||||
return err;
|
||||
}
|
||||
|
||||
/* Disable all misc interrupts */
|
||||
nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
|
||||
|
||||
/* Clear pending misc interrupts */
|
||||
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
|
||||
MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
|
||||
|
||||
/* Enable all misc interrupts */
|
||||
nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
|
||||
|
||||
|
||||
/* Disable all legacy interrupts */
|
||||
nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
|
||||
|
||||
/* Clear pending legacy interrupts */
|
||||
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
|
||||
MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
|
||||
|
||||
/* Enable all legacy interrupts */
|
||||
nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
|
||||
|
||||
/* Enable the bridge config interrupt */
|
||||
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
|
||||
BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *node = pcie->dev->of_node;
|
||||
struct resource *res;
|
||||
const char *type;
|
||||
|
||||
/* Check for device type */
|
||||
type = of_get_property(node, "device_type", NULL);
|
||||
if (!type || strcmp(type, "pci")) {
|
||||
dev_err(pcie->dev, "invalid \"device_type\" %s\n", type);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
|
||||
pcie->breg_base = devm_ioremap_resource(pcie->dev, res);
|
||||
if (IS_ERR(pcie->breg_base))
|
||||
return PTR_ERR(pcie->breg_base);
|
||||
pcie->phys_breg_base = res->start;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
|
||||
pcie->pcireg_base = devm_ioremap_resource(pcie->dev, res);
|
||||
if (IS_ERR(pcie->pcireg_base))
|
||||
return PTR_ERR(pcie->pcireg_base);
|
||||
pcie->phys_pcie_reg_base = res->start;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
|
||||
pcie->ecam_base = devm_ioremap_resource(pcie->dev, res);
|
||||
if (IS_ERR(pcie->ecam_base))
|
||||
return PTR_ERR(pcie->ecam_base);
|
||||
pcie->phys_ecam_base = res->start;
|
||||
|
||||
/* Get intx IRQ number */
|
||||
pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
|
||||
if (pcie->irq_intx < 0) {
|
||||
dev_err(&pdev->dev, "failed to get intx IRQ %d\n",
|
||||
pcie->irq_intx);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
irq_set_chained_handler_and_data(pcie->irq_intx,
|
||||
nwl_pcie_leg_handler, pcie);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id nwl_pcie_of_match[] = {
|
||||
{ .compatible = "xlnx,nwl-pcie-2.11", },
|
||||
{}
|
||||
};
|
||||
|
||||
static int nwl_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct nwl_pcie *pcie;
|
||||
struct pci_bus *bus;
|
||||
struct pci_bus *child;
|
||||
int err;
|
||||
resource_size_t iobase = 0;
|
||||
LIST_HEAD(res);
|
||||
|
||||
pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
|
||||
if (!pcie)
|
||||
return -ENOMEM;
|
||||
|
||||
pcie->dev = &pdev->dev;
|
||||
pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
|
||||
|
||||
err = nwl_pcie_parse_dt(pcie, pdev);
|
||||
if (err) {
|
||||
dev_err(pcie->dev, "Parsing DT failed\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
err = nwl_pcie_bridge_init(pcie);
|
||||
if (err) {
|
||||
dev_err(pcie->dev, "HW Initalization failed\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
err = of_pci_get_host_bridge_resources(node, 0, 0xff, &res, &iobase);
|
||||
if (err) {
|
||||
pr_err("Getting bridge resources failed\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
err = nwl_pcie_init_irq_domain(pcie);
|
||||
if (err) {
|
||||
dev_err(pcie->dev, "Failed creating IRQ Domain\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
bus = pci_create_root_bus(&pdev->dev, pcie->root_busno,
|
||||
&nwl_pcie_ops, pcie, &res);
|
||||
if (!bus)
|
||||
return -ENOMEM;
|
||||
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
||||
err = nwl_pcie_enable_msi(pcie, bus);
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev,
|
||||
"failed to enable MSI support: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
}
|
||||
pci_scan_child_bus(bus);
|
||||
pci_assign_unassigned_bus_resources(bus);
|
||||
list_for_each_entry(child, &bus->children, node)
|
||||
pcie_bus_configure_settings(child);
|
||||
pci_bus_add_devices(bus);
|
||||
platform_set_drvdata(pdev, pcie);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nwl_pcie_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct nwl_pcie *pcie = platform_get_drvdata(pdev);
|
||||
|
||||
nwl_pcie_free_irq_domain(pcie);
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver nwl_pcie_driver = {
|
||||
.driver = {
|
||||
.name = "nwl-pcie",
|
||||
.of_match_table = nwl_pcie_of_match,
|
||||
},
|
||||
.probe = nwl_pcie_probe,
|
||||
.remove = nwl_pcie_remove,
|
||||
};
|
||||
module_platform_driver(nwl_pcie_driver);
|
||||
|
||||
MODULE_AUTHOR("Xilinx, Inc");
|
||||
MODULE_DESCRIPTION("NWL PCIe driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue