tools build: Add Makefile.include
To ease up build framework code setup for users. More shared code will be added in the following patches. Signed-off-by: Jiri Olsa <jolsa@kernel.org> Cc: David Ahern <dsahern@gmail.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1443004442-32660-2-git-send-email-jolsa@kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>hifive-unleashed-5.1
Jiri Olsa
Arnaldo Carvalho de Melo
parent
dc240c5dc2
commit
ab6201d09b
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@ -11,8 +11,9 @@ Unlike the kernel we don't have a single build object 'obj-y' list that where
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we setup source objects, but we support more. This allows one 'Build' file to
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carry a sources list for multiple build objects.
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a) Build framework makefiles
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----------------------------
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Build framework makefiles
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-------------------------
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The build framework consists of 2 Makefiles:
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@ -23,7 +24,7 @@ While the 'Build.include' file contains just some generic definitions, the
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'Makefile.build' file is the makefile used from the outside. It's
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interface/usage is following:
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$ make -f tools/build/Makefile srctree=$(KSRC) dir=$(DIR) obj=$(OBJECT)
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$ make -f tools/build/Makefile.build srctree=$(KSRC) dir=$(DIR) obj=$(OBJECT)
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where:
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@ -38,8 +39,9 @@ called $(OBJECT)-in.o:
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which includes all compiled sources described in 'Build' makefiles.
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a) Build makefiles
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------------------
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Build makefiles
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---------------
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The user supplies 'Build' makefiles that contains a objects list, and connects
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the build to nested directories.
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@ -95,8 +97,24 @@ It's only a matter of 2 single commands to create the final binaries:
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You can check the 'ex' example in 'tools/build/tests/ex' for more details.
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b) Rules
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--------
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Makefile.include
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----------------
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The tools/build/Makefile.include makefile could be included
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via user makefiles to get usefull definitions.
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It defines following interface:
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- build macro definition:
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build := -f $(srctree)/tools/build/Makefile.build dir=. obj
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to make it easier to invoke build like:
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make $(build)=ex
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Rules
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-----
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The build framework provides standard compilation rules to handle .S and .c
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compilation.
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@ -104,8 +122,9 @@ compilation.
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It's possible to include special rule if needed (like we do for flex or bison
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code generation).
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c) CFLAGS
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---------
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CFLAGS
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------
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It's possible to alter the standard object C flags in the following way:
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@ -115,8 +134,8 @@ It's possible to alter the standard object C flags in the following way:
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This C flags changes has the scope of the Build makefile they are defined in.
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d) Dependencies
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---------------
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Dependencies
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------------
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For each built object file 'a.o' the '.a.cmd' is created and holds:
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@ -130,8 +149,8 @@ All existing '.cmd' files are included in the Build process to follow properly
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the dependencies and trigger a rebuild when necessary.
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e) Single rules
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---------------
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Single rules
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------------
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It's possible to build single object file by choice, like:
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@ -0,0 +1 @@
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build := -f $(srctree)/tools/build/Makefile.build dir=. obj
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@ -3,7 +3,8 @@ export CC := gcc
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export LD := ld
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export AR := ar
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build := -f $(srctree)/tools/build/Makefile.build dir=. obj
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include $(srctree)/tools/build/Makefile.include
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ex: ex-in.o libex-in.o
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gcc -o $@ $^
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@ -21,10 +21,10 @@ CFLAGS += -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64
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RM = rm -f
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build := -f $(srctree)/tools/build/Makefile.build dir=. obj
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API_IN := $(OUTPUT)libapi-in.o
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export srctree OUTPUT CC LD CFLAGS V
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include $(srctree)/tools/build/Makefile.include
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all: $(LIBFILE)
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@ -124,7 +124,7 @@ endif
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MAKEOVERRIDES=
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export srctree OUTPUT CC LD CFLAGS V
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build := -f $(srctree)/tools/build/Makefile.build dir=. obj
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include $(srctree)/tools/build/Makefile.include
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BPF_IN := $(OUTPUT)libbpf-in.o
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LIB_FILE := $(addprefix $(OUTPUT),$(LIB_FILE))
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@ -94,7 +94,7 @@ else
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endif
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export srctree OUTPUT CC LD CFLAGS V
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build := -f $(srctree)/tools/build/Makefile.build dir=. obj
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include $(srctree)/tools/build/Makefile.include
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do_compile_shared_library = \
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($(print_shared_lib_compile) \
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@ -297,7 +297,7 @@ strip: $(PROGRAMS) $(OUTPUT)perf
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PERF_IN := $(OUTPUT)perf-in.o
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export srctree OUTPUT RM CC LD AR CFLAGS V BISON FLEX AWK
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build := -f $(srctree)/tools/build/Makefile.build dir=. obj
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include $(srctree)/tools/build/Makefile.include
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$(PERF_IN): $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)common-cmds.h FORCE
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$(Q)$(MAKE) $(build)=perf
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