dmaengine: dw: lazy allocation of dma descriptors
This patch changes the driver to allocate DMA descriptors when needed. This stops memory resources to be wasted and letting them sit idle in the free_list structure when the device doesn't need it... This also solves the problem, that a driver has to guess the number of how many descriptors it needs to allocate in advance. Currently, the dma engine will just fail when put under load by sata_dwc_460ex. Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>hifive-unleashed-5.1
Christian Lamparter
Vinod Koul
parent
925a7d045e
commit
ab703f818a
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@ -58,13 +58,6 @@
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| DWC_CTLL_SMS(_sms)); \
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})
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/*
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* Number of descriptors to allocate for each channel. This should be
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* made configurable somehow; preferably, the clients (at least the
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* ones using slave transfers) should be able to give us a hint.
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*/
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#define NR_DESCS_PER_CHANNEL 64
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/* The set of bus widths supported by the DMA controller */
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#define DW_DMA_BUSWIDTHS \
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BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
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@ -84,51 +77,65 @@ static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
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return to_dw_desc(dwc->active_list.next);
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}
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static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
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static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct dw_desc *desc, *_desc;
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struct dw_desc *ret = NULL;
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unsigned int i = 0;
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unsigned long flags;
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struct dw_desc *desc = txd_to_dw_desc(tx);
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struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
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dma_cookie_t cookie;
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unsigned long flags;
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spin_lock_irqsave(&dwc->lock, flags);
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list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
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i++;
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if (async_tx_test_ack(&desc->txd)) {
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list_del(&desc->desc_node);
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ret = desc;
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break;
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}
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dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
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}
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cookie = dma_cookie_assign(tx);
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/*
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* REVISIT: We should attempt to chain as many descriptors as
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* possible, perhaps even appending to those already submitted
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* for DMA. But this is hard to do in a race-free manner.
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*/
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list_add_tail(&desc->desc_node, &dwc->queue);
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spin_unlock_irqrestore(&dwc->lock, flags);
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dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n",
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__func__, desc->txd.cookie);
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dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
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return ret;
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return cookie;
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}
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static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
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{
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struct dw_dma *dw = to_dw_dma(dwc->chan.device);
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struct dw_desc *desc;
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dma_addr_t phys;
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desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys);
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if (!desc)
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return NULL;
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dwc->descs_allocated++;
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INIT_LIST_HEAD(&desc->tx_list);
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dma_async_tx_descriptor_init(&desc->txd, &dwc->chan);
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desc->txd.tx_submit = dwc_tx_submit;
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desc->txd.flags = DMA_CTRL_ACK;
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desc->txd.phys = phys;
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return desc;
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}
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/*
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* Move a descriptor, including any children, to the free list.
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* `desc' must not be on any lists.
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*/
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static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
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{
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unsigned long flags;
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struct dw_dma *dw = to_dw_dma(dwc->chan.device);
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struct dw_desc *child, *_next;
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if (desc) {
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struct dw_desc *child;
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if (unlikely(!desc))
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return;
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spin_lock_irqsave(&dwc->lock, flags);
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list_for_each_entry(child, &desc->tx_list, desc_node)
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dev_vdbg(chan2dev(&dwc->chan),
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"moving child desc %p to freelist\n",
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child);
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list_splice_init(&desc->tx_list, &dwc->free_list);
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dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
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list_add(&desc->desc_node, &dwc->free_list);
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spin_unlock_irqrestore(&dwc->lock, flags);
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list_for_each_entry_safe(child, _next, &desc->tx_list, desc_node) {
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list_del(&child->desc_node);
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dma_pool_free(dw->desc_pool, child, child->txd.phys);
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dwc->descs_allocated--;
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}
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dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
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dwc->descs_allocated--;
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}
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static void dwc_initialize(struct dw_dma_chan *dwc)
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@ -297,11 +304,7 @@ dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
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list_for_each_entry(child, &desc->tx_list, desc_node)
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async_tx_ack(&child->txd);
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async_tx_ack(&desc->txd);
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list_splice_init(&desc->tx_list, &dwc->free_list);
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list_move(&desc->desc_node, &dwc->free_list);
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dma_descriptor_unmap(txd);
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dwc_desc_put(dwc, desc);
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spin_unlock_irqrestore(&dwc->lock, flags);
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if (callback)
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@ -663,30 +666,6 @@ static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
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/*----------------------------------------------------------------------*/
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static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct dw_desc *desc = txd_to_dw_desc(tx);
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struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
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dma_cookie_t cookie;
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unsigned long flags;
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spin_lock_irqsave(&dwc->lock, flags);
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cookie = dma_cookie_assign(tx);
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/*
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* REVISIT: We should attempt to chain as many descriptors as
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* possible, perhaps even appending to those already submitted
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* for DMA. But this is hard to do in a race-free manner.
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*/
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dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie);
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list_add_tail(&desc->desc_node, &dwc->queue);
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spin_unlock_irqrestore(&dwc->lock, flags);
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return cookie;
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}
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static struct dma_async_tx_descriptor *
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dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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size_t len, unsigned long flags)
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@ -1159,9 +1138,6 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
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{
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struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
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struct dw_dma *dw = to_dw_dma(chan->device);
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struct dw_desc *desc;
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int i;
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unsigned long flags;
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dev_vdbg(chan2dev(chan), "%s\n", __func__);
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@ -1192,48 +1168,13 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
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dw_dma_on(dw);
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dw->in_use |= dwc->mask;
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spin_lock_irqsave(&dwc->lock, flags);
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i = dwc->descs_allocated;
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while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
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dma_addr_t phys;
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spin_unlock_irqrestore(&dwc->lock, flags);
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desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
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if (!desc)
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goto err_desc_alloc;
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memset(desc, 0, sizeof(struct dw_desc));
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INIT_LIST_HEAD(&desc->tx_list);
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dma_async_tx_descriptor_init(&desc->txd, chan);
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desc->txd.tx_submit = dwc_tx_submit;
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desc->txd.flags = DMA_CTRL_ACK;
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desc->txd.phys = phys;
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dwc_desc_put(dwc, desc);
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spin_lock_irqsave(&dwc->lock, flags);
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i = ++dwc->descs_allocated;
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}
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spin_unlock_irqrestore(&dwc->lock, flags);
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dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
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return i;
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err_desc_alloc:
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dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
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return i;
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return 0;
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}
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static void dwc_free_chan_resources(struct dma_chan *chan)
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{
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struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
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struct dw_dma *dw = to_dw_dma(chan->device);
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struct dw_desc *desc, *_desc;
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unsigned long flags;
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LIST_HEAD(list);
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@ -1246,8 +1187,6 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
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BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
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spin_lock_irqsave(&dwc->lock, flags);
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list_splice_init(&dwc->free_list, &list);
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dwc->descs_allocated = 0;
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/* Clear custom channel configuration */
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dwc->src_id = 0;
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@ -1270,11 +1209,6 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
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if (!dw->in_use)
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dw_dma_off(dw);
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list_for_each_entry_safe(desc, _desc, &list, desc_node) {
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dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
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dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
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}
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dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
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}
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@ -1406,9 +1340,6 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
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retval = ERR_PTR(-ENOMEM);
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if (periods > NR_DESCS_PER_CHANNEL)
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goto out_err;
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cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
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if (!cdesc)
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goto out_err;
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@ -1641,7 +1572,6 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
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INIT_LIST_HEAD(&dwc->active_list);
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INIT_LIST_HEAD(&dwc->queue);
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INIT_LIST_HEAD(&dwc->free_list);
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channel_clear_bit(dw, CH_EN, dwc->mask);
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@ -236,7 +236,6 @@ struct dw_dma_chan {
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unsigned long flags;
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struct list_head active_list;
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struct list_head queue;
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struct list_head free_list;
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struct dw_cyclic_desc *cdesc;
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unsigned int descs_allocated;
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