serial: sh-sci: Kill off bitrotted H8/300 support.
h8300 has never been updated upstream to support the conversion to the driver model (which happened mid-2.5), and it doesn't seem likely that it ever will. Kill off the remaining bitrotted support to reduce the maintenance burden going forward. Signed-off-by: Paul Mundt <lethal@linux-sh.org>hifive-unleashed-5.1
Paul Mundt
parent
0792644d22
commit
ab7cfb5548
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@ -974,7 +974,7 @@ config SERIAL_IP22_ZILOG_CONSOLE
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config SERIAL_SH_SCI
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tristate "SuperH SCI(F) serial port support"
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depends on HAVE_CLK && (SUPERH || H8300 || ARCH_SHMOBILE)
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depends on HAVE_CLK && (SUPERH || ARCH_SHMOBILE)
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select SERIAL_CORE
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config SERIAL_SH_SCI_NR_UARTS
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@ -54,10 +54,6 @@
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#include <asm/sh_bios.h>
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#endif
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#ifdef CONFIG_H8300
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#include <asm/gpio.h>
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#endif
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#include "sh-sci.h"
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struct sci_port {
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@ -164,23 +160,7 @@ static void sci_poll_put_char(struct uart_port *port, unsigned char c)
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}
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#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
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#if defined(__H8300H__) || defined(__H8300S__)
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static void sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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int ch = (port->mapbase - SMR0) >> 3;
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/* set DDR regs */
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H8300_GPIO_DDR(h8300_sci_pins[ch].port,
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h8300_sci_pins[ch].rx,
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H8300_GPIO_INPUT);
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H8300_GPIO_DDR(h8300_sci_pins[ch].port,
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h8300_sci_pins[ch].tx,
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H8300_GPIO_OUTPUT);
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/* tx mark output*/
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H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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if (port->mapbase == 0xA4400000) {
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@ -1863,14 +1843,8 @@ static int __devinit serial_console_setup(struct console *co, char *options)
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if (options)
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uart_parse_options(options, &baud, &parity, &bits, &flow);
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ret = uart_set_options(port, co, baud, parity, bits, flow);
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#if defined(__H8300H__) || defined(__H8300S__)
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/* disable rx interrupt */
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if (ret == 0)
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sci_stop_rx(port);
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#endif
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/* TODO: disable clock */
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return ret;
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return uart_set_options(port, co, baud, parity, bits, flow);
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}
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static struct console serial_console = {
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@ -2,13 +2,6 @@
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#include <linux/io.h>
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#include <linux/gpio.h>
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#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
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#include <asm/regs306x.h>
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#endif
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#if defined(CONFIG_H8S2678)
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#include <asm/regs267x.h>
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7708) || \
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@ -72,10 +65,6 @@
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#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
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# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
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# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
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#elif defined(CONFIG_H8S2678)
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# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
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# define SCSPTR0 0xfe4b0020
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# define SCIF_ORER 0x0001
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@ -223,17 +212,6 @@
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} \
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}
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#ifdef CONFIG_H8300
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/* h8300 don't have SCIF */
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#define CPU_SCIF_FNS(name) \
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static inline unsigned int sci_##name##_in(struct uart_port *port) \
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{ \
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return 0; \
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} \
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static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
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{ \
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}
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#else
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#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
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static inline unsigned int sci_##name##_in(struct uart_port *port) \
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{ \
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@ -243,7 +221,6 @@
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{ \
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SCI_OUT(scif_size, scif_offset, value); \
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}
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#endif
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#define CPU_SCI_FNS(name, sci_offset, sci_size) \
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static inline unsigned int sci_##name##_in(struct uart_port* port) \
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@ -262,8 +239,7 @@
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defined(CONFIG_ARCH_SH7372)
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#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
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sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
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h8_sci_offset, h8_sci_size) \
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sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
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CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
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#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
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CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
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@ -282,19 +258,11 @@
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CPU_SCIF_FNS(name, scif_offset, scif_size)
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#else
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#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
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sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
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h8_sci_offset, h8_sci_size) \
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sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
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CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
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#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
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CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
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#endif
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#elif defined(__H8300H__) || defined(__H8300S__)
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#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
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sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
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h8_sci_offset, h8_sci_size) \
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CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
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#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
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CPU_SCIF_FNS(name)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
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defined(CONFIG_CPU_SUBTYPE_SH7724)
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#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
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@ -303,8 +271,7 @@
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CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
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#else
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#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
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sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
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h8_sci_offset, h8_sci_size) \
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sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
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CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
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#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
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CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
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@ -353,14 +320,14 @@ SCIF_FNS(SCFCR, 0x18, 16)
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SCIF_FNS(SCFDR, 0x1c, 16)
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SCIF_FNS(SCLSR, 0x24, 16)
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#else
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/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
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/* name off sz off sz off sz off sz off sz*/
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SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
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SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
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SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
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SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
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SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
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SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
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/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 */
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/* name off sz off sz off sz off sz */
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SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16)
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SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8)
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SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16)
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SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8)
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SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16)
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SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8)
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SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
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#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
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defined(CONFIG_CPU_SUBTYPE_SH7780) || \
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@ -390,48 +357,6 @@ SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
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#define sci_in(port, reg) sci_##reg##_in(port)
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#define sci_out(port, reg, value) sci_##reg##_out(port, value)
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/* H8/300 series SCI pins assignment */
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#if defined(__H8300H__) || defined(__H8300S__)
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static const struct __attribute__((packed)) {
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int port; /* GPIO port no */
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unsigned short rx,tx; /* GPIO bit no */
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} h8300_sci_pins[] = {
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#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
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{ /* SCI0 */
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.port = H8300_GPIO_P9,
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.rx = H8300_GPIO_B2,
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.tx = H8300_GPIO_B0,
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},
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{ /* SCI1 */
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.port = H8300_GPIO_P9,
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.rx = H8300_GPIO_B3,
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.tx = H8300_GPIO_B1,
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},
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{ /* SCI2 */
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.port = H8300_GPIO_PB,
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.rx = H8300_GPIO_B7,
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.tx = H8300_GPIO_B6,
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}
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#elif defined(CONFIG_H8S2678)
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{ /* SCI0 */
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.port = H8300_GPIO_P3,
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.rx = H8300_GPIO_B2,
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.tx = H8300_GPIO_B0,
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},
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{ /* SCI1 */
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.port = H8300_GPIO_P3,
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.rx = H8300_GPIO_B3,
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.tx = H8300_GPIO_B1,
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},
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{ /* SCI2 */
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.port = H8300_GPIO_P5,
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.rx = H8300_GPIO_B1,
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.tx = H8300_GPIO_B0,
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}
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#endif
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};
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7708) || \
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@ -454,12 +379,6 @@ static inline int sci_rxd_in(struct uart_port *port)
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return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
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return 1;
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}
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#elif defined(__H8300H__) || defined(__H8300S__)
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static inline int sci_rxd_in(struct uart_port *port)
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{
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int ch = (port->mapbase - SMR0) >> 3;
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return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
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}
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#else /* default case for non-SCI processors */
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static inline int sci_rxd_in(struct uart_port *port)
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{
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