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EDAC, altera: Add Arria10 Ethernet EDAC support 

Add Altera Arria10 Ethernet FIFO memory EDAC support. Update to support
a common compatibility string for all Ethernet FIFOs in the DT.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1466603939-7526-8-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
hifive-unleashed-5.1
Thor Thayer 2016-06-22 08:58:58 -05:00 committed by Borislav Petkov
parent 1166fde93d
commit ab8c1e0fb0
3 changed files with 45 additions and 2 deletions
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7
drivers/edac/Kconfig
View File

@ -391,6 +391,13 @@ config EDAC_ALTERA_OCRAM
Support for error detection and correction on the
Altera On-Chip RAM Memory for Altera SoCs.
config EDAC_ALTERA_ETHERNET
bool "Altera Ethernet FIFO ECC"
depends on EDAC_ALTERA=y
help
Support for error detection and correction on the
Altera Ethernet FIFO Memory for Altera SoCs.
config EDAC_SYNOPSYS
tristate "Synopsys DDR Memory Controller"
depends on EDAC_MM_EDAC && ARCH_ZYNQ

37
drivers/edac/altera_edac.c
View File

@ -1258,6 +1258,33 @@ static const struct edac_device_prv_data a10_l2ecc_data = {
#endif /* CONFIG_EDAC_ALTERA_L2C */
/********************* Ethernet Device Functions ********************/
#ifdef CONFIG_EDAC_ALTERA_ETHERNET
static const struct edac_device_prv_data a10_enetecc_data = {
.setup = altr_check_ecc_deps,
.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
.dbgfs_name = "altr_trigger",
.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
.ce_set_mask = ALTR_A10_ECC_TSERRA,
.ue_set_mask = ALTR_A10_ECC_TDERRA,
.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
.ecc_irq_handler = altr_edac_a10_ecc_irq,
.inject_fops = &altr_edac_a10_device_inject_fops,
};
static int __init socfpga_init_ethernet_ecc(void)
{
return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
}
early_initcall(socfpga_init_ethernet_ecc);
#endif /* CONFIG_EDAC_ALTERA_ETHERNET */
/********************* Arria10 EDAC Device Functions *************************/
static const struct of_device_id altr_edac_a10_device_of_match[] = {
#ifdef CONFIG_EDAC_ALTERA_L2C
@ -1266,6 +1293,10 @@ static const struct of_device_id altr_edac_a10_device_of_match[] = {
#ifdef CONFIG_EDAC_ALTERA_OCRAM
{ .compatible = "altr,socfpga-a10-ocram-ecc",
.data = &a10_ocramecc_data },
#endif
#ifdef CONFIG_EDAC_ALTERA_ETHERNET
{ .compatible = "altr,socfpga-eth-mac-ecc",
.data = &a10_enetecc_data },
#endif
{},
};
@ -1555,8 +1586,10 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
continue;
if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc"))
altr_edac_a10_device_add(edac, child);
else if (of_device_is_compatible(child,
"altr,socfpga-a10-ocram-ecc"))
else if ((of_device_is_compatible(child,
"altr,socfpga-a10-ocram-ecc")) ||
(of_device_is_compatible(child,
"altr,socfpga-eth-mac-ecc")))
altr_edac_a10_device_add(edac, child);
else if (of_device_is_compatible(child,
"altr,sdram-edac-a10"))

3
drivers/edac/altera_edac.h
View File

@ -285,6 +285,9 @@ struct altr_sdram_mc_data {
/* Arria 10 OCRAM ECC Management Group Defines */
#define ALTR_A10_OCRAM_ECC_EN_CTL (BIT(1) | BIT(0))
/* Arria 10 Ethernet ECC Management Group Defines */
#define ALTR_A10_COMMON_ECC_EN_CTL BIT(0)
/* A10 ECC Controller memory initialization timeout */
#define ALTR_A10_ECC_INIT_WATCHDOG_10US 10000