sparc32,sun4m: irq, smp files cleanup
- drop filename in file header - drop unused includes - add description of sun4m interrupts (from davem) - add KERN_* to printk - fix spaces => tabs - add spaces after reserved words - drop all externs, they are now in header files This is partly based on a patch from: David Miller <davem@davemloft.net> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
Sam Ravnborg
David S. Miller
parent
e787098cfe
commit
aba20a8295
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@ -1,5 +1,5 @@
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/* sun4m_irq.c
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* arch/sparc/kernel/sun4m_irq.c:
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/*
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* sun4m irq support
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*
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* djhr: Hacked out of irq.c into a CPU dependent version.
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*
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@ -9,36 +9,92 @@
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* Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
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*/
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#include <linux/errno.h>
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#include <linux/linkage.h>
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#include <linux/kernel_stat.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/ptrace.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/psr.h>
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#include <asm/vaddrs.h>
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#include <asm/timer.h>
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#include <asm/openprom.h>
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#include <asm/oplib.h>
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#include <asm/traps.h>
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#include <asm/pgalloc.h>
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#include <asm/pgtable.h>
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#include <asm/smp.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/cacheflush.h>
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#include "irq.h"
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#include "kernel.h"
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/* Sample sun4m IRQ layout:
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*
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* 0x22 - Power
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* 0x24 - ESP SCSI
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* 0x26 - Lance ethernet
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* 0x2b - Floppy
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* 0x2c - Zilog uart
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* 0x32 - SBUS level 0
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* 0x33 - Parallel port, SBUS level 1
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* 0x35 - SBUS level 2
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* 0x37 - SBUS level 3
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* 0x39 - Audio, Graphics card, SBUS level 4
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* 0x3b - SBUS level 5
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* 0x3d - SBUS level 6
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*
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* Each interrupt source has a mask bit in the interrupt registers.
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* When the mask bit is set, this blocks interrupt deliver. So you
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* clear the bit to enable the interrupt.
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*
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* Interrupts numbered less than 0x10 are software triggered interrupts
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* and unused by Linux.
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*
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* Interrupt level assignment on sun4m:
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*
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* level source
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* ------------------------------------------------------------
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* 1 softint-1
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* 2 softint-2, VME/SBUS level 1
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* 3 softint-3, VME/SBUS level 2
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* 4 softint-4, onboard SCSI
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* 5 softint-5, VME/SBUS level 3
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* 6 softint-6, onboard ETHERNET
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* 7 softint-7, VME/SBUS level 4
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* 8 softint-8, onboard VIDEO
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* 9 softint-9, VME/SBUS level 5, Module Interrupt
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* 10 softint-10, system counter/timer
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* 11 softint-11, VME/SBUS level 6, Floppy
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* 12 softint-12, Keyboard/Mouse, Serial
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* 13 softint-13, VME/SBUS level 7, ISDN Audio
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* 14 softint-14, per-processor counter/timer
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* 15 softint-15, Asynchronous Errors (broadcast)
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*
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* Each interrupt source is masked distinctly in the sun4m interrupt
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* registers. The PIL level alone is therefore ambiguous, since multiple
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* interrupt sources map to a single PIL.
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*
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* This ambiguity is resolved in the 'intr' property for device nodes
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* in the OF device tree. Each 'intr' property entry is composed of
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* two 32-bit words. The first word is the IRQ priority value, which
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* is what we're intersted in. The second word is the IRQ vector, which
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* is unused.
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*
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* The low 4 bits of the IRQ priority indicate the PIL, and the upper
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* 4 bits indicate onboard vs. SBUS leveled vs. VME leveled. 0x20
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* means onboard, 0x30 means SBUS leveled, and 0x40 means VME leveled.
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*
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* For example, an 'intr' IRQ priority value of 0x24 is onboard SCSI
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* whereas a value of 0x33 is SBUS level 2. Here are some sample
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* 'intr' property IRQ priority values from ss4, ss5, ss10, ss20, and
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* Tadpole S3 GX systems.
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*
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* esp: 0x24 onboard ESP SCSI
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* le: 0x26 onboard Lance ETHERNET
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* p9100: 0x32 SBUS level 1 P9100 video
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* bpp: 0x33 SBUS level 2 BPP parallel port device
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* DBRI: 0x39 SBUS level 5 DBRI ISDN audio
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* SUNW,leo: 0x39 SBUS level 5 LEO video
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* pcmcia: 0x3b SBUS level 6 PCMCIA controller
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* uctrl: 0x3b SBUS level 6 UCTRL device
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* modem: 0x3d SBUS level 7 MODEM
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* zs: 0x2c onboard keyboard/mouse/serial
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* floppy: 0x2b onboard Floppy
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* power: 0x22 onboard power device (XXX unknown mask bit XXX)
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*/
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struct sun4m_irq_percpu {
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u32 pending;
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@ -99,59 +155,6 @@ struct sun4m_irq_global __iomem *sun4m_irq_global;
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#define OBP_INT_LEVEL_SBUS 0x30
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#define OBP_INT_LEVEL_VME 0x40
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/* Interrupt level assignment on sun4m:
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*
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* level source
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* ------------------------------------------------------------
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* 1 softint-1
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* 2 softint-2, VME/SBUS level 1
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* 3 softint-3, VME/SBUS level 2
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* 4 softint-4, onboard SCSI
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* 5 softint-5, VME/SBUS level 3
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* 6 softint-6, onboard ETHERNET
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* 7 softint-7, VME/SBUS level 4
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* 8 softint-8, onboard VIDEO
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* 9 softint-9, VME/SBUS level 5, Module Interrupt
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* 10 softint-10, system counter/timer
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* 11 softint-11, VME/SBUS level 6, Floppy
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* 12 softint-12, Keyboard/Mouse, Serial
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* 13 softint-13, VME/SBUS level 7, ISDN Audio
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* 14 softint-14, per-processor counter/timer
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* 15 softint-15, Asynchronous Errors (broadcast)
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*
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* Each interrupt source is masked distinctly in the sun4m interrupt
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* registers. The PIL level alone is therefore ambiguous, since multiple
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* interrupt sources map to a single PIL.
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*
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* This ambiguity is resolved in the 'intr' property for device nodes
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* in the OF device tree. Each 'intr' property entry is composed of
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* two 32-bit words. The first word is the IRQ priority value, which
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* is what we're intersted in. The second word is the IRQ vector, which
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* is unused.
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*
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* The low 4 bits of the IRQ priority indicate the PIL, and the upper
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* 4 bits indicate onboard vs. SBUS leveled vs. VME leveled. 0x20
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* means onboard, 0x30 means SBUS leveled, and 0x40 means VME leveled.
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*
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* For example, an 'intr' IRQ priority value of 0x24 is onboard SCSI
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* whereas a value of 0x33 is SBUS level 2. Here are some sample
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* 'intr' property IRQ priority values from ss4, ss5, ss10, ss20, and
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* Tadpole S3 GX systems.
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*
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* esp: 0x24 onboard ESP SCSI
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* le: 0x26 onboard Lance ETHERNET
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* p9100: 0x32 SBUS level 1 P9100 video
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* bpp: 0x33 SBUS level 2 BPP parallel port device
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* DBRI: 0x39 SBUS level 5 DBRI ISDN audio
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* SUNW,leo: 0x39 SBUS level 5 LEO video
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* pcmcia: 0x3b SBUS level 6 PCMCIA controller
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* uctrl: 0x3b SBUS level 6 UCTRL device
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* modem: 0x3d SBUS level 7 MODEM
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* zs: 0x2c onboard keyboard/mouse/serial
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* floppy: 0x2b onboard Floppy
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* power: 0x22 onboard power device (XXX unknown mask bit XXX)
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*/
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static unsigned long irq_mask[0x50] = {
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/* SMP */
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0, SUN4M_SOFT_INT(1),
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@ -260,7 +263,7 @@ static unsigned long cpu_pil_to_imask[16] = {
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/*12*/ SUN4M_INT_SERIAL | SUN4M_INT_KBDMS,
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/*13*/ SUN4M_INT_SBUS(6) | SUN4M_INT_VME(6) | SUN4M_INT_AUDIO,
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/*14*/ SUN4M_INT_E14,
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/*15*/ SUN4M_INT_ERROR
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/*15*/ SUN4M_INT_ERROR,
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};
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/* We assume the caller has disabled local interrupts when these are called,
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@ -280,12 +283,14 @@ static void sun4m_enable_pil_irq(unsigned int pil)
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static void sun4m_send_ipi(int cpu, int level)
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{
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unsigned long mask = sun4m_get_irqmask(level);
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sbus_writel(mask, &sun4m_irq_percpu[cpu]->set);
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}
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static void sun4m_clear_ipi(int cpu, int level)
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{
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unsigned long mask = sun4m_get_irqmask(level);
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sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear);
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}
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@ -407,7 +412,6 @@ static void __init sun4m_init_timers(irq_handler_t counter_fn)
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#ifdef CONFIG_SMP
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{
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unsigned long flags;
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extern unsigned long lvl14_save[4];
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struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
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/* For SMP we use the level 14 ticker, however the bootup code
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@ -1,59 +1,22 @@
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/* sun4m_smp.c: Sparc SUN4M SMP support.
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/*
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* sun4m SMP support.
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*
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* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
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*/
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#include <asm/head.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/threads.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <linux/swap.h>
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#include <linux/profile.h>
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#include <linux/delay.h>
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#include <linux/cpu.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm/irq_regs.h>
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#include <asm/ptrace.h>
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#include <asm/atomic.h>
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#include <asm/irq.h>
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#include <asm/page.h>
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#include <asm/pgalloc.h>
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#include <asm/pgtable.h>
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#include <asm/oplib.h>
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#include <asm/cpudata.h>
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#include "irq.h"
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#include "kernel.h"
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#define IRQ_CROSS_CALL 15
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extern ctxd_t *srmmu_ctx_table_phys;
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extern volatile unsigned long cpu_callin_map[NR_CPUS];
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extern unsigned char boot_cpu_id;
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extern cpumask_t smp_commenced_mask;
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extern int __smp4m_processor_id(void);
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/*#define SMP_DEBUG*/
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#ifdef SMP_DEBUG
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#define SMP_PRINTK(x) printk x
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#else
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#define SMP_PRINTK(x)
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#endif
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static inline unsigned long
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swap_ulong(volatile unsigned long *ptr, unsigned long val)
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{
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@ -64,7 +27,6 @@ swap_ulong(volatile unsigned long *ptr, unsigned long val)
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}
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static void smp_setup_percpu_timer(void);
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extern void cpu_probe(void);
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void __cpuinit smp4m_callin(void)
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{
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@ -119,9 +81,6 @@ void __cpuinit smp4m_callin(void)
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/*
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* Cycle through the processors asking the PROM to start each one.
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*/
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extern struct linux_prom_registers smp_penguin_ctable;
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void __init smp4m_boot_cpus(void)
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{
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smp_setup_percpu_timer();
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@ -130,7 +89,6 @@ void __init smp4m_boot_cpus(void)
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int __cpuinit smp4m_boot_one_cpu(int i)
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{
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extern unsigned long sun4m_cpu_startup;
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unsigned long *entry = &sun4m_cpu_startup;
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struct task_struct *p;
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int timeout;
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@ -142,7 +100,7 @@ int __cpuinit smp4m_boot_one_cpu(int i)
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p = fork_idle(i);
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current_set[i] = task_thread_info(p);
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/* See trampoline.S for details... */
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entry += ((i-1) * 3);
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entry += ((i - 1) * 3);
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/*
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* Initialize the contexts table
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@ -154,20 +112,19 @@ int __cpuinit smp4m_boot_one_cpu(int i)
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smp_penguin_ctable.reg_size = 0;
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/* whirrr, whirrr, whirrrrrrrrr... */
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printk("Starting CPU %d at %p\n", i, entry);
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printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
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local_flush_cache_all();
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prom_startcpu(cpu_node,
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&smp_penguin_ctable, 0, (char *)entry);
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prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry);
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/* wheee... it's going... */
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for(timeout = 0; timeout < 10000; timeout++) {
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if(cpu_callin_map[i])
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for (timeout = 0; timeout < 10000; timeout++) {
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if (cpu_callin_map[i])
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break;
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udelay(200);
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}
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if (!(cpu_callin_map[i])) {
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printk("Processor %d is stuck.\n", i);
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printk(KERN_ERR "Processor %d is stuck.\n", i);
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return -ENODEV;
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}
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@ -202,6 +159,7 @@ void __init smp4m_smp_done(void)
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void smp4m_irq_rotate(int cpu)
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{
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int next = cpu_data(cpu).next;
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if (next != cpu)
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set_irq_udt(next);
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}
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@ -243,7 +201,7 @@ static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
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cpu_clear(smp_processor_id(), mask);
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cpus_and(mask, cpu_online_map, mask);
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for(i = 0; i < ncpus; i++) {
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for (i = 0; i < ncpus; i++) {
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if (cpu_isset(i, mask)) {
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ccall_info.processors_in[i] = 0;
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ccall_info.processors_out[i] = 0;
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@ -262,19 +220,18 @@ static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
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do {
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if (!cpu_isset(i, mask))
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continue;
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while(!ccall_info.processors_in[i])
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while (!ccall_info.processors_in[i])
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barrier();
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} while(++i < ncpus);
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} while (++i < ncpus);
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i = 0;
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do {
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if (!cpu_isset(i, mask))
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continue;
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while(!ccall_info.processors_out[i])
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while (!ccall_info.processors_out[i])
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barrier();
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} while(++i < ncpus);
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} while (++i < ncpus);
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}
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spin_unlock_irqrestore(&cross_call_lock, flags);
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}
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@ -289,8 +246,6 @@ void smp4m_cross_call_irq(void)
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ccall_info.processors_out[i] = 1;
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}
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extern void sun4m_clear_profile_irq(int cpu);
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void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
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{
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struct pt_regs *old_regs;
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@ -302,7 +257,7 @@ void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
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profile_tick(CPU_PROFILING);
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if(!--prof_counter(cpu)) {
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if (!--prof_counter(cpu)) {
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int user = user_mode(regs);
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irq_enter();
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@ -314,8 +269,6 @@ void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
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set_irq_regs(old_regs);
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}
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extern unsigned int lvl14_resolution;
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static void __cpuinit smp_setup_percpu_timer(void)
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{
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int cpu = smp_processor_id();
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@ -323,7 +276,7 @@ static void __cpuinit smp_setup_percpu_timer(void)
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prof_counter(cpu) = prof_multiplier(cpu) = 1;
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load_profile_irq(cpu, lvl14_resolution);
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if(cpu == boot_cpu_id)
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if (cpu == boot_cpu_id)
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enable_pil_irq(14);
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}
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