x86/platform/UV: Add Support for UV4 Hubless NMIs
Merge new UV Hubless NMI support into existing UV NMI handler. Signed-off-by: Mike Travis <travis@sgi.com> Reviewed-by: Russ Anderson <rja@hpe.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Dimitri Sivanich <sivanich@hpe.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/20170125163517.585269837@asylum.americas.sgi.com Signed-off-by: Ingo Molnar <mingo@kernel.org>hifive-unleashed-5.1
travis@sgi.com
Ingo Molnar
parent
74862b03b4
commit
abdf1df6bc
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@ -772,6 +772,7 @@ static inline int uv_num_possible_blades(void)
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/* Per Hub NMI support */
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extern void uv_nmi_setup(void);
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extern void uv_nmi_setup_hubless(void);
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/* BMC sets a bit this MMR non-zero before sending an NMI */
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#define UVH_NMI_MMR UVH_SCRATCH5
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@ -799,6 +800,8 @@ struct uv_hub_nmi_s {
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atomic_t read_mmr_count; /* count of MMR reads */
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atomic_t nmi_count; /* count of true UV NMIs */
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unsigned long nmi_value; /* last value read from NMI MMR */
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bool hub_present; /* false means UV hubless system */
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bool pch_owner; /* indicates this hub owns PCH */
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};
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struct uv_cpu_nmi_s {
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@ -1514,6 +1514,8 @@ void __init uv_system_init(void)
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if (is_uv_system())
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uv_system_init_hub();
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else
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uv_nmi_setup_hubless();
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}
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apic_driver(apic_x2apic_uv_x);
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@ -67,6 +67,18 @@ static struct uv_hub_nmi_s **uv_hub_nmi_list;
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DEFINE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi);
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EXPORT_PER_CPU_SYMBOL_GPL(uv_cpu_nmi);
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/* UV hubless values */
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#define NMI_CONTROL_PORT 0x70
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#define NMI_DUMMY_PORT 0x71
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#define GPI_NMI_STS_GPP_D_0 0x164
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#define GPI_NMI_ENA_GPP_D_0 0x174
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#define STS_GPP_D_0_MASK 0x1
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#define PAD_CFG_DW0_GPP_D_0 0x4c0
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#define GPIROUTNMI (1ul << 17)
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#define PCH_PCR_GPIO_1_BASE 0xfdae0000ul
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#define PCH_PCR_GPIO_ADDRESS(offset) (int *)((u64)(pch_base) | (u64)(offset))
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static u64 *pch_base;
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static unsigned long nmi_mmr;
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static unsigned long nmi_mmr_clear;
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static unsigned long nmi_mmr_pending;
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@ -144,6 +156,19 @@ module_param_named(wait_count, uv_nmi_wait_count, int, 0644);
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static int uv_nmi_retry_count = 500;
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module_param_named(retry_count, uv_nmi_retry_count, int, 0644);
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static bool uv_pch_intr_enable = true;
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static bool uv_pch_intr_now_enabled;
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module_param_named(pch_intr_enable, uv_pch_intr_enable, bool, 0644);
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static int uv_nmi_debug;
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module_param_named(debug, uv_nmi_debug, int, 0644);
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#define nmi_debug(fmt, ...) \
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do { \
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if (uv_nmi_debug) \
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pr_info(fmt, ##__VA_ARGS__); \
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} while (0)
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/*
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* Valid NMI Actions:
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* "dump" - dump process stack for each cpu
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@ -191,6 +216,77 @@ static inline void uv_local_mmr_clear_nmi(void)
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uv_write_local_mmr(nmi_mmr_clear, nmi_mmr_pending);
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}
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/*
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* UV hubless NMI handler functions
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*/
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static inline void uv_reassert_nmi(void)
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{
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/* (from arch/x86/include/asm/mach_traps.h) */
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outb(0x8f, NMI_CONTROL_PORT);
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inb(NMI_DUMMY_PORT); /* dummy read */
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outb(0x0f, NMI_CONTROL_PORT);
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inb(NMI_DUMMY_PORT); /* dummy read */
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}
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static void uv_init_hubless_pch_io(int offset, int mask, int data)
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{
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int *addr = PCH_PCR_GPIO_ADDRESS(offset);
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int readd = readl(addr);
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if (mask) { /* OR in new data */
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int writed = (readd & ~mask) | data;
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nmi_debug("UV:PCH: %p = %x & %x | %x (%x)\n",
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addr, readd, ~mask, data, writed);
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writel(writed, addr);
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} else if (readd & data) { /* clear status bit */
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nmi_debug("UV:PCH: %p = %x\n", addr, data);
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writel(data, addr);
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}
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(void)readl(addr); /* flush write data */
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}
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static void uv_nmi_setup_hubless_intr(void)
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{
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uv_pch_intr_now_enabled = uv_pch_intr_enable;
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uv_init_hubless_pch_io(
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PAD_CFG_DW0_GPP_D_0, GPIROUTNMI,
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uv_pch_intr_now_enabled ? GPIROUTNMI : 0);
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nmi_debug("UV:NMI: GPP_D_0 interrupt %s\n",
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uv_pch_intr_now_enabled ? "enabled" : "disabled");
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}
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static int uv_nmi_test_hubless(struct uv_hub_nmi_s *hub_nmi)
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{
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int *pstat = PCH_PCR_GPIO_ADDRESS(GPI_NMI_STS_GPP_D_0);
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int status = *pstat;
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hub_nmi->nmi_value = status;
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atomic_inc(&hub_nmi->read_mmr_count);
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if (!(status & STS_GPP_D_0_MASK)) /* Not a UV external NMI */
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return 0;
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*pstat = STS_GPP_D_0_MASK; /* Is a UV NMI: clear GPP_D_0 status */
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(void)*pstat; /* flush write */
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return 1;
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}
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static int uv_test_nmi(struct uv_hub_nmi_s *hub_nmi)
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{
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if (hub_nmi->hub_present)
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return uv_nmi_test_mmr(hub_nmi);
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if (hub_nmi->pch_owner) /* Only PCH owner can check status */
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return uv_nmi_test_hubless(hub_nmi);
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return -1;
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}
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/*
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* If first cpu in on this hub, set hub_nmi "in_nmi" and "owner" values and
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* return true. If first cpu in on the system, set global "in_nmi" flag.
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@ -214,6 +310,7 @@ static int uv_check_nmi(struct uv_hub_nmi_s *hub_nmi)
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{
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int cpu = smp_processor_id();
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int nmi = 0;
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int nmi_detected = 0;
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local64_inc(&uv_nmi_count);
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this_cpu_inc(uv_cpu_nmi.queries);
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@ -224,20 +321,26 @@ static int uv_check_nmi(struct uv_hub_nmi_s *hub_nmi)
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break;
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if (raw_spin_trylock(&hub_nmi->nmi_lock)) {
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nmi_detected = uv_test_nmi(hub_nmi);
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/* check hub MMR NMI flag */
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if (uv_nmi_test_mmr(hub_nmi)) {
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/* check flag for UV external NMI */
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if (nmi_detected > 0) {
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uv_set_in_nmi(cpu, hub_nmi);
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nmi = 1;
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break;
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}
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/* MMR NMI flag is clear */
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/* A non-PCH node in a hubless system waits for NMI */
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else if (nmi_detected < 0)
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goto slave_wait;
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/* MMR/PCH NMI flag is clear */
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raw_spin_unlock(&hub_nmi->nmi_lock);
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} else {
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/* wait a moment for the hub nmi locker to set flag */
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cpu_relax();
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/* Wait a moment for the HUB NMI locker to set flag */
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slave_wait: cpu_relax();
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udelay(uv_nmi_slave_delay);
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/* re-check hub in_nmi flag */
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@ -246,13 +349,20 @@ static int uv_check_nmi(struct uv_hub_nmi_s *hub_nmi)
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break;
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}
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/* check if this BMC missed setting the MMR NMI flag */
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/*
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* Check if this BMC missed setting the MMR NMI flag (or)
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* UV hubless system where only PCH owner can check flag
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*/
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if (!nmi) {
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nmi = atomic_read(&uv_in_nmi);
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if (nmi)
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uv_set_in_nmi(cpu, hub_nmi);
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}
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/* If we're holding the hub lock, release it now */
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if (nmi_detected < 0)
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raw_spin_unlock(&hub_nmi->nmi_lock);
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} while (0);
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if (!nmi)
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@ -269,7 +379,10 @@ static inline void uv_clear_nmi(int cpu)
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if (cpu == atomic_read(&hub_nmi->cpu_owner)) {
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atomic_set(&hub_nmi->cpu_owner, -1);
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atomic_set(&hub_nmi->in_nmi, 0);
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uv_local_mmr_clear_nmi();
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if (hub_nmi->hub_present)
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uv_local_mmr_clear_nmi();
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else
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uv_reassert_nmi();
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raw_spin_unlock(&hub_nmi->nmi_lock);
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}
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}
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@ -297,11 +410,12 @@ static void uv_nmi_cleanup_mask(void)
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}
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}
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/* Loop waiting as cpus enter nmi handler */
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/* Loop waiting as cpus enter NMI handler */
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static int uv_nmi_wait_cpus(int first)
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{
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int i, j, k, n = num_online_cpus();
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int last_k = 0, waiting = 0;
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int cpu = smp_processor_id();
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if (first) {
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cpumask_copy(uv_nmi_cpu_mask, cpu_online_mask);
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@ -310,6 +424,12 @@ static int uv_nmi_wait_cpus(int first)
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k = n - cpumask_weight(uv_nmi_cpu_mask);
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}
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/* PCH NMI causes only one cpu to respond */
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if (first && uv_pch_intr_now_enabled) {
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cpumask_clear_cpu(cpu, uv_nmi_cpu_mask);
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return n - k - 1;
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}
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udelay(uv_nmi_initial_delay);
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for (i = 0; i < uv_nmi_retry_count; i++) {
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int loop_delay = uv_nmi_loop_delay;
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@ -358,7 +478,7 @@ static void uv_nmi_wait(int master)
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break;
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/* if not all made it in, send IPI NMI to them */
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pr_alert("UV: Sending NMI IPI to %d non-responding CPUs: %*pbl\n",
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pr_alert("UV: Sending NMI IPI to %d CPUs: %*pbl\n",
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cpumask_weight(uv_nmi_cpu_mask),
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cpumask_pr_args(uv_nmi_cpu_mask));
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@ -538,7 +658,7 @@ static inline int uv_nmi_kdb_reason(void)
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#else /* !CONFIG_KGDB_KDB */
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static inline int uv_nmi_kdb_reason(void)
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{
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/* Insure user is expecting to attach gdb remote */
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/* Ensure user is expecting to attach gdb remote */
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if (uv_nmi_action_is("kgdb"))
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return 0;
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@ -626,15 +746,18 @@ int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
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/* Pause as all cpus enter the NMI handler */
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uv_nmi_wait(master);
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/* Dump state of each cpu */
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if (uv_nmi_action_is("ips") || uv_nmi_action_is("dump"))
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/* Process actions other than "kdump": */
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if (uv_nmi_action_is("ips") || uv_nmi_action_is("dump")) {
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uv_nmi_dump_state(cpu, regs, master);
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/* Call KGDB/KDB if enabled */
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else if (uv_nmi_action_is("kdb") || uv_nmi_action_is("kgdb"))
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} else if (uv_nmi_action_is("kdb") || uv_nmi_action_is("kgdb")) {
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uv_call_kgdb_kdb(cpu, regs, master);
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} else {
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if (master)
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pr_alert("UV: unknown NMI action: %s\n", uv_nmi_action);
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uv_nmi_sync_exit(master);
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}
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/* Clear per_cpu "in nmi" flag */
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/* Clear per_cpu "in_nmi" flag */
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this_cpu_write(uv_cpu_nmi.state, UV_NMI_STATE_OUT);
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/* Clear MMR NMI flag on each hub */
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@ -648,6 +771,7 @@ int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
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atomic_set(&uv_nmi_cpu, -1);
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atomic_set(&uv_in_nmi, 0);
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atomic_set(&uv_nmi_kexec_failed, 0);
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atomic_set(&uv_nmi_slave_continue, SLAVE_CLEAR);
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}
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uv_nmi_touch_watchdogs();
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@ -697,28 +821,53 @@ void uv_nmi_init(void)
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apic_write(APIC_LVT1, value);
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}
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void uv_nmi_setup(void)
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/* Setup HUB NMI info */
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void __init uv_nmi_setup_common(bool hubbed)
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{
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int size = sizeof(void *) * (1 << NODES_SHIFT);
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int cpu, nid;
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int cpu;
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/* Setup hub nmi info */
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uv_nmi_setup_mmrs();
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uv_hub_nmi_list = kzalloc(size, GFP_KERNEL);
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pr_info("UV: NMI hub list @ 0x%p (%d)\n", uv_hub_nmi_list, size);
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nmi_debug("UV: NMI hub list @ 0x%p (%d)\n", uv_hub_nmi_list, size);
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BUG_ON(!uv_hub_nmi_list);
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size = sizeof(struct uv_hub_nmi_s);
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for_each_present_cpu(cpu) {
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nid = cpu_to_node(cpu);
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int nid = cpu_to_node(cpu);
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if (uv_hub_nmi_list[nid] == NULL) {
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uv_hub_nmi_list[nid] = kzalloc_node(size,
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GFP_KERNEL, nid);
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BUG_ON(!uv_hub_nmi_list[nid]);
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raw_spin_lock_init(&(uv_hub_nmi_list[nid]->nmi_lock));
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atomic_set(&uv_hub_nmi_list[nid]->cpu_owner, -1);
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uv_hub_nmi_list[nid]->hub_present = hubbed;
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uv_hub_nmi_list[nid]->pch_owner = (nid == 0);
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}
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uv_hub_nmi_per(cpu) = uv_hub_nmi_list[nid];
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}
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BUG_ON(!alloc_cpumask_var(&uv_nmi_cpu_mask, GFP_KERNEL));
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uv_register_nmi_notifier();
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}
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/* Setup for UV Hub systems */
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void __init uv_nmi_setup(void)
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{
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uv_nmi_setup_mmrs();
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uv_nmi_setup_common(true);
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uv_register_nmi_notifier();
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pr_info("UV: Hub NMI enabled\n");
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}
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/* Setup for UV Hubless systems */
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void __init uv_nmi_setup_hubless(void)
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{
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uv_nmi_setup_common(false);
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pch_base = xlate_dev_mem_ptr(PCH_PCR_GPIO_1_BASE);
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nmi_debug("UV: PCH base:%p from 0x%lx, GPP_D_0\n",
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pch_base, PCH_PCR_GPIO_1_BASE);
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uv_init_hubless_pch_io(GPI_NMI_ENA_GPP_D_0,
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STS_GPP_D_0_MASK, STS_GPP_D_0_MASK);
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uv_nmi_setup_hubless_intr();
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/* Ensure NMI enabled in Processor Interface Reg: */
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uv_reassert_nmi();
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uv_register_nmi_notifier();
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pr_info("UV: Hubless NMI enabled\n");
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}
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