phy: intel: Add driver support for ComboPhy
ComboPhy subsystem provides PHYs for various controllers like PCIe, SATA and EMAC. Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> Acked-By: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/7b313826f46b9006a3ba98c0613e8f88f293a074.1589868358.git.eswara.kota@linux.intel.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Dilip Kota
Kishon Vijay Abraham I
parent
1d51a2caa7
commit
ac0a95a3ea
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@ -2,6 +2,20 @@
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#
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# Phy drivers for Intel Lightning Mountain(LGM) platform
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#
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config PHY_INTEL_COMBO
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bool "Intel ComboPHY driver"
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depends on X86 || COMPILE_TEST
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depends on OF && HAS_IOMEM
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select MFD_SYSCON
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select GENERIC_PHY
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select REGMAP
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help
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Enable this to support Intel ComboPhy.
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This driver configures ComboPhy subsystem on Intel gateway
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chipsets which provides PHYs for various controllers, EMAC,
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SATA and PCIe.
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config PHY_INTEL_EMMC
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tristate "Intel EMMC PHY driver"
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depends on X86 || COMPILE_TEST
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@ -1,2 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_PHY_INTEL_COMBO) += phy-intel-combo.o
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obj-$(CONFIG_PHY_INTEL_EMMC) += phy-intel-emmc.o
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632
drivers/phy/intel/phy-intel-combo.c
Normal file
632
drivers/phy/intel/phy-intel-combo.c
Normal file
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@ -0,0 +1,632 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel Combo-PHY driver
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*
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* Copyright (C) 2019-2020 Intel Corporation.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/iopoll.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <dt-bindings/phy/phy.h>
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#define PCIE_PHY_GEN_CTRL 0x00
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#define PCIE_PHY_CLK_PAD BIT(17)
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#define PAD_DIS_CFG 0x174
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#define PCS_XF_ATE_OVRD_IN_2 0x3008
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#define ADAPT_REQ_MSK GENMASK(5, 4)
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#define PCS_XF_RX_ADAPT_ACK 0x3010
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#define RX_ADAPT_ACK_BIT BIT(0)
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#define CR_ADDR(addr, lane) (((addr) + (lane) * 0x100) << 2)
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#define REG_COMBO_MODE(x) ((x) * 0x200)
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#define REG_CLK_DISABLE(x) ((x) * 0x200 + 0x124)
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#define COMBO_PHY_ID(x) ((x)->parent->id)
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#define PHY_ID(x) ((x)->id)
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#define CLK_100MHZ 100000000
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#define CLK_156_25MHZ 156250000
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static const unsigned long intel_iphy_clk_rates[] = {
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CLK_100MHZ, CLK_156_25MHZ, CLK_100MHZ,
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};
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enum {
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PHY_0,
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PHY_1,
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PHY_MAX_NUM
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};
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/*
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* Clock Register bit fields to enable clocks
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* for ComboPhy according to the mode.
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*/
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enum intel_phy_mode {
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PHY_PCIE_MODE = 0,
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PHY_XPCS_MODE,
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PHY_SATA_MODE,
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};
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/* ComboPhy mode Register values */
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enum intel_combo_mode {
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PCIE0_PCIE1_MODE = 0,
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PCIE_DL_MODE,
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RXAUI_MODE,
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XPCS0_XPCS1_MODE,
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SATA0_SATA1_MODE,
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};
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enum aggregated_mode {
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PHY_SL_MODE,
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PHY_DL_MODE,
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};
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struct intel_combo_phy;
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struct intel_cbphy_iphy {
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struct phy *phy;
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struct intel_combo_phy *parent;
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struct reset_control *app_rst;
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u32 id;
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};
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struct intel_combo_phy {
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struct device *dev;
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struct clk *core_clk;
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unsigned long clk_rate;
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void __iomem *app_base;
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void __iomem *cr_base;
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struct regmap *syscfg;
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struct regmap *hsiocfg;
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u32 id;
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u32 bid;
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struct reset_control *phy_rst;
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struct reset_control *core_rst;
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struct intel_cbphy_iphy iphy[PHY_MAX_NUM];
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enum intel_phy_mode phy_mode;
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enum aggregated_mode aggr_mode;
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u32 init_cnt;
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struct mutex lock;
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};
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static int intel_cbphy_iphy_enable(struct intel_cbphy_iphy *iphy, bool set)
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{
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struct intel_combo_phy *cbphy = iphy->parent;
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u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id);
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u32 val;
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/* Register: 0 is enable, 1 is disable */
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val = set ? 0 : mask;
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return regmap_update_bits(cbphy->hsiocfg, REG_CLK_DISABLE(cbphy->bid),
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mask, val);
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}
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static int intel_cbphy_pcie_refclk_cfg(struct intel_cbphy_iphy *iphy, bool set)
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{
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struct intel_combo_phy *cbphy = iphy->parent;
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u32 mask = BIT(cbphy->id * 2 + iphy->id);
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u32 val;
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/* Register: 0 is enable, 1 is disable */
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val = set ? 0 : mask;
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return regmap_update_bits(cbphy->syscfg, PAD_DIS_CFG, mask, val);
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}
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static inline void combo_phy_w32_off_mask(void __iomem *base, unsigned int reg,
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u32 mask, u32 val)
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{
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u32 reg_val;
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reg_val = readl(base + reg);
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reg_val &= ~mask;
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reg_val |= FIELD_PREP(mask, val);
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writel(reg_val, base + reg);
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}
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static int intel_cbphy_iphy_cfg(struct intel_cbphy_iphy *iphy,
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int (*phy_cfg)(struct intel_cbphy_iphy *))
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{
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struct intel_combo_phy *cbphy = iphy->parent;
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int ret;
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ret = phy_cfg(iphy);
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if (ret)
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return ret;
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if (cbphy->aggr_mode != PHY_DL_MODE)
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return 0;
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return phy_cfg(&cbphy->iphy[PHY_1]);
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}
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static int intel_cbphy_pcie_en_pad_refclk(struct intel_cbphy_iphy *iphy)
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{
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struct intel_combo_phy *cbphy = iphy->parent;
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int ret;
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ret = intel_cbphy_pcie_refclk_cfg(iphy, true);
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if (ret) {
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dev_err(cbphy->dev, "Failed to enable PCIe pad refclk\n");
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return ret;
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}
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if (cbphy->init_cnt)
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return 0;
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combo_phy_w32_off_mask(cbphy->app_base, PCIE_PHY_GEN_CTRL,
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PCIE_PHY_CLK_PAD, 0);
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/* Delay for stable clock PLL */
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usleep_range(50, 100);
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return 0;
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}
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static int intel_cbphy_pcie_dis_pad_refclk(struct intel_cbphy_iphy *iphy)
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{
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struct intel_combo_phy *cbphy = iphy->parent;
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int ret;
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ret = intel_cbphy_pcie_refclk_cfg(iphy, false);
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if (ret) {
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dev_err(cbphy->dev, "Failed to disable PCIe pad refclk\n");
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return ret;
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}
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if (cbphy->init_cnt)
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return 0;
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combo_phy_w32_off_mask(cbphy->app_base, PCIE_PHY_GEN_CTRL,
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PCIE_PHY_CLK_PAD, 1);
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return 0;
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}
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static int intel_cbphy_set_mode(struct intel_combo_phy *cbphy)
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{
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enum intel_combo_mode cb_mode = PHY_PCIE_MODE;
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enum aggregated_mode aggr = cbphy->aggr_mode;
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struct device *dev = cbphy->dev;
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enum intel_phy_mode mode;
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int ret;
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mode = cbphy->phy_mode;
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switch (mode) {
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case PHY_PCIE_MODE:
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cb_mode = (aggr == PHY_DL_MODE) ? PCIE_DL_MODE : PCIE0_PCIE1_MODE;
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break;
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case PHY_XPCS_MODE:
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cb_mode = (aggr == PHY_DL_MODE) ? RXAUI_MODE : XPCS0_XPCS1_MODE;
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break;
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case PHY_SATA_MODE:
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if (aggr == PHY_DL_MODE) {
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dev_err(dev, "Mode:%u not support dual lane!\n", mode);
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return -EINVAL;
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}
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cb_mode = SATA0_SATA1_MODE;
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break;
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}
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ret = regmap_write(cbphy->hsiocfg, REG_COMBO_MODE(cbphy->bid), cb_mode);
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if (ret)
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dev_err(dev, "Failed to set ComboPhy mode: %d\n", ret);
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return ret;
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}
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static void intel_cbphy_rst_assert(struct intel_combo_phy *cbphy)
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{
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reset_control_assert(cbphy->core_rst);
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reset_control_assert(cbphy->phy_rst);
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}
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static void intel_cbphy_rst_deassert(struct intel_combo_phy *cbphy)
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{
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reset_control_deassert(cbphy->core_rst);
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reset_control_deassert(cbphy->phy_rst);
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/* Delay to ensure reset process is done */
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usleep_range(10, 20);
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}
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static int intel_cbphy_iphy_power_on(struct intel_cbphy_iphy *iphy)
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{
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struct intel_combo_phy *cbphy = iphy->parent;
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int ret;
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if (!cbphy->init_cnt) {
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ret = clk_prepare_enable(cbphy->core_clk);
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if (ret) {
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dev_err(cbphy->dev, "Clock enable failed!\n");
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return ret;
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}
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ret = clk_set_rate(cbphy->core_clk, cbphy->clk_rate);
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if (ret) {
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dev_err(cbphy->dev, "Clock freq set to %lu failed!\n",
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cbphy->clk_rate);
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goto clk_err;
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}
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intel_cbphy_rst_assert(cbphy);
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intel_cbphy_rst_deassert(cbphy);
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ret = intel_cbphy_set_mode(cbphy);
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if (ret)
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goto clk_err;
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}
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ret = intel_cbphy_iphy_enable(iphy, true);
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if (ret) {
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dev_err(cbphy->dev, "Failed enabling PHY core\n");
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goto clk_err;
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}
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ret = reset_control_deassert(iphy->app_rst);
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if (ret) {
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dev_err(cbphy->dev, "PHY(%u:%u) reset deassert failed!\n",
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COMBO_PHY_ID(iphy), PHY_ID(iphy));
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goto clk_err;
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}
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/* Delay to ensure reset process is done */
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udelay(1);
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return 0;
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clk_err:
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clk_disable_unprepare(cbphy->core_clk);
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return ret;
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}
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static int intel_cbphy_iphy_power_off(struct intel_cbphy_iphy *iphy)
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{
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struct intel_combo_phy *cbphy = iphy->parent;
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int ret;
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ret = reset_control_assert(iphy->app_rst);
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if (ret) {
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dev_err(cbphy->dev, "PHY(%u:%u) reset assert failed!\n",
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COMBO_PHY_ID(iphy), PHY_ID(iphy));
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return ret;
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}
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ret = intel_cbphy_iphy_enable(iphy, false);
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if (ret) {
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dev_err(cbphy->dev, "Failed disabling PHY core\n");
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return ret;
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}
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if (cbphy->init_cnt)
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return 0;
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clk_disable_unprepare(cbphy->core_clk);
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intel_cbphy_rst_assert(cbphy);
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return 0;
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}
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static int intel_cbphy_init(struct phy *phy)
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{
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struct intel_cbphy_iphy *iphy = phy_get_drvdata(phy);
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struct intel_combo_phy *cbphy = iphy->parent;
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int ret;
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mutex_lock(&cbphy->lock);
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ret = intel_cbphy_iphy_cfg(iphy, intel_cbphy_iphy_power_on);
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if (ret)
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goto err;
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if (cbphy->phy_mode == PHY_PCIE_MODE) {
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ret = intel_cbphy_iphy_cfg(iphy, intel_cbphy_pcie_en_pad_refclk);
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if (ret)
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goto err;
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}
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cbphy->init_cnt++;
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err:
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mutex_unlock(&cbphy->lock);
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return ret;
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}
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static int intel_cbphy_exit(struct phy *phy)
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{
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struct intel_cbphy_iphy *iphy = phy_get_drvdata(phy);
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struct intel_combo_phy *cbphy = iphy->parent;
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int ret;
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mutex_lock(&cbphy->lock);
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cbphy->init_cnt--;
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if (cbphy->phy_mode == PHY_PCIE_MODE) {
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ret = intel_cbphy_iphy_cfg(iphy, intel_cbphy_pcie_dis_pad_refclk);
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if (ret)
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goto err;
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}
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ret = intel_cbphy_iphy_cfg(iphy, intel_cbphy_iphy_power_off);
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err:
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mutex_unlock(&cbphy->lock);
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return ret;
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}
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static int intel_cbphy_calibrate(struct phy *phy)
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{
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struct intel_cbphy_iphy *iphy = phy_get_drvdata(phy);
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struct intel_combo_phy *cbphy = iphy->parent;
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void __iomem *cr_base = cbphy->cr_base;
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int val, ret, id;
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if (cbphy->phy_mode != PHY_XPCS_MODE)
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return 0;
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id = PHY_ID(iphy);
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/* trigger auto RX adaptation */
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combo_phy_w32_off_mask(cr_base, CR_ADDR(PCS_XF_ATE_OVRD_IN_2, id),
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ADAPT_REQ_MSK, 3);
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/* Wait RX adaptation to finish */
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ret = readl_poll_timeout(cr_base + CR_ADDR(PCS_XF_RX_ADAPT_ACK, id),
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val, val & RX_ADAPT_ACK_BIT, 10, 5000);
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if (ret)
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dev_err(cbphy->dev, "RX Adaptation failed!\n");
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else
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dev_dbg(cbphy->dev, "RX Adaptation success!\n");
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/* Stop RX adaptation */
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combo_phy_w32_off_mask(cr_base, CR_ADDR(PCS_XF_ATE_OVRD_IN_2, id),
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ADAPT_REQ_MSK, 0);
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return ret;
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}
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static int intel_cbphy_fwnode_parse(struct intel_combo_phy *cbphy)
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{
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struct device *dev = cbphy->dev;
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struct platform_device *pdev = to_platform_device(dev);
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struct fwnode_handle *fwnode = dev_fwnode(dev);
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struct fwnode_reference_args ref;
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int ret;
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u32 val;
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cbphy->core_clk = devm_clk_get(dev, NULL);
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if (IS_ERR(cbphy->core_clk)) {
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ret = PTR_ERR(cbphy->core_clk);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "Get clk failed:%d!\n", ret);
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return ret;
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}
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cbphy->core_rst = devm_reset_control_get_optional(dev, "core");
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if (IS_ERR(cbphy->core_rst)) {
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ret = PTR_ERR(cbphy->core_rst);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "Get core reset control err: %d!\n", ret);
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return ret;
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}
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cbphy->phy_rst = devm_reset_control_get_optional(dev, "phy");
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if (IS_ERR(cbphy->phy_rst)) {
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ret = PTR_ERR(cbphy->phy_rst);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "Get PHY reset control err: %d!\n", ret);
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return ret;
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}
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cbphy->iphy[0].app_rst = devm_reset_control_get_optional(dev, "iphy0");
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if (IS_ERR(cbphy->iphy[0].app_rst)) {
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ret = PTR_ERR(cbphy->iphy[0].app_rst);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "Get phy0 reset control err: %d!\n", ret);
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return ret;
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}
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|
||||
cbphy->iphy[1].app_rst = devm_reset_control_get_optional(dev, "iphy1");
|
||||
if (IS_ERR(cbphy->iphy[1].app_rst)) {
|
||||
ret = PTR_ERR(cbphy->iphy[1].app_rst);
|
||||
if (ret != -EPROBE_DEFER)
|
||||
dev_err(dev, "Get phy1 reset control err: %d!\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
cbphy->app_base = devm_platform_ioremap_resource_byname(pdev, "app");
|
||||
if (IS_ERR(cbphy->app_base))
|
||||
return PTR_ERR(cbphy->app_base);
|
||||
|
||||
cbphy->cr_base = devm_platform_ioremap_resource_byname(pdev, "core");
|
||||
if (IS_ERR(cbphy->cr_base))
|
||||
return PTR_ERR(cbphy->cr_base);
|
||||
|
||||
/*
|
||||
* syscfg and hsiocfg variables stores the handle of the registers set
|
||||
* in which ComboPhy subsytem specific registers are subset. Using
|
||||
* Register map framework to access the registers set.
|
||||
*/
|
||||
ret = fwnode_property_get_reference_args(fwnode, "intel,syscfg", NULL,
|
||||
1, 0, &ref);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
cbphy->id = ref.args[0];
|
||||
cbphy->syscfg = device_node_to_regmap(to_of_node(ref.fwnode));
|
||||
fwnode_handle_put(ref.fwnode);
|
||||
|
||||
ret = fwnode_property_get_reference_args(fwnode, "intel,hsio", NULL, 1,
|
||||
0, &ref);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
cbphy->bid = ref.args[0];
|
||||
cbphy->hsiocfg = device_node_to_regmap(to_of_node(ref.fwnode));
|
||||
fwnode_handle_put(ref.fwnode);
|
||||
|
||||
ret = fwnode_property_read_u32_array(fwnode, "intel,phy-mode", &val, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
switch (val) {
|
||||
case PHY_TYPE_PCIE:
|
||||
cbphy->phy_mode = PHY_PCIE_MODE;
|
||||
break;
|
||||
|
||||
case PHY_TYPE_SATA:
|
||||
cbphy->phy_mode = PHY_SATA_MODE;
|
||||
break;
|
||||
|
||||
case PHY_TYPE_XPCS:
|
||||
cbphy->phy_mode = PHY_XPCS_MODE;
|
||||
break;
|
||||
|
||||
default:
|
||||
dev_err(dev, "Invalid PHY mode: %u\n", val);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
cbphy->clk_rate = intel_iphy_clk_rates[cbphy->phy_mode];
|
||||
|
||||
if (fwnode_property_present(fwnode, "intel,aggregation"))
|
||||
cbphy->aggr_mode = PHY_DL_MODE;
|
||||
else
|
||||
cbphy->aggr_mode = PHY_SL_MODE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct phy_ops intel_cbphy_ops = {
|
||||
.init = intel_cbphy_init,
|
||||
.exit = intel_cbphy_exit,
|
||||
.calibrate = intel_cbphy_calibrate,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static struct phy *intel_cbphy_xlate(struct device *dev,
|
||||
struct of_phandle_args *args)
|
||||
{
|
||||
struct intel_combo_phy *cbphy = dev_get_drvdata(dev);
|
||||
u32 iphy_id;
|
||||
|
||||
if (args->args_count < 1) {
|
||||
dev_err(dev, "Invalid number of arguments\n");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
iphy_id = args->args[0];
|
||||
if (iphy_id >= PHY_MAX_NUM) {
|
||||
dev_err(dev, "Invalid phy instance %d\n", iphy_id);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
if (cbphy->aggr_mode == PHY_DL_MODE && iphy_id == PHY_1) {
|
||||
dev_err(dev, "Invalid. ComboPhy is in Dual lane mode %d\n", iphy_id);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return cbphy->iphy[iphy_id].phy;
|
||||
}
|
||||
|
||||
static int intel_cbphy_create(struct intel_combo_phy *cbphy)
|
||||
{
|
||||
struct phy_provider *phy_provider;
|
||||
struct device *dev = cbphy->dev;
|
||||
struct intel_cbphy_iphy *iphy;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < PHY_MAX_NUM; i++) {
|
||||
iphy = &cbphy->iphy[i];
|
||||
iphy->parent = cbphy;
|
||||
iphy->id = i;
|
||||
|
||||
/* In dual lane mode skip phy creation for the second phy */
|
||||
if (cbphy->aggr_mode == PHY_DL_MODE && iphy->id == PHY_1)
|
||||
continue;
|
||||
|
||||
iphy->phy = devm_phy_create(dev, NULL, &intel_cbphy_ops);
|
||||
if (IS_ERR(iphy->phy)) {
|
||||
dev_err(dev, "PHY[%u:%u]: create PHY instance failed!\n",
|
||||
COMBO_PHY_ID(iphy), PHY_ID(iphy));
|
||||
|
||||
return PTR_ERR(iphy->phy);
|
||||
}
|
||||
|
||||
phy_set_drvdata(iphy->phy, iphy);
|
||||
}
|
||||
|
||||
dev_set_drvdata(dev, cbphy);
|
||||
phy_provider = devm_of_phy_provider_register(dev, intel_cbphy_xlate);
|
||||
if (IS_ERR(phy_provider))
|
||||
dev_err(dev, "Register PHY provider failed!\n");
|
||||
|
||||
return PTR_ERR_OR_ZERO(phy_provider);
|
||||
}
|
||||
|
||||
static int intel_cbphy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct intel_combo_phy *cbphy;
|
||||
int ret;
|
||||
|
||||
cbphy = devm_kzalloc(dev, sizeof(*cbphy), GFP_KERNEL);
|
||||
if (!cbphy)
|
||||
return -ENOMEM;
|
||||
|
||||
cbphy->dev = dev;
|
||||
cbphy->init_cnt = 0;
|
||||
mutex_init(&cbphy->lock);
|
||||
ret = intel_cbphy_fwnode_parse(cbphy);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
platform_set_drvdata(pdev, cbphy);
|
||||
|
||||
return intel_cbphy_create(cbphy);
|
||||
}
|
||||
|
||||
static int intel_cbphy_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct intel_combo_phy *cbphy = platform_get_drvdata(pdev);
|
||||
|
||||
intel_cbphy_rst_assert(cbphy);
|
||||
clk_disable_unprepare(cbphy->core_clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_intel_cbphy_match[] = {
|
||||
{ .compatible = "intel,combo-phy" },
|
||||
{ .compatible = "intel,combophy-lgm" },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver intel_cbphy_driver = {
|
||||
.probe = intel_cbphy_probe,
|
||||
.remove = intel_cbphy_remove,
|
||||
.driver = {
|
||||
.name = "intel-combo-phy",
|
||||
.of_match_table = of_intel_cbphy_match,
|
||||
}
|
||||
};
|
||||
|
||||
module_platform_driver(intel_cbphy_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Intel Combo-phy driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in a new issue