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MLK-17190 driver: soc: Fix audio bus mode clock rate on imx8mq 

If the system is currently in low bus mode, if the audio device
request the audio bus mode, the NOC, AHB and AXI bus clock rate
will be set wrongly, then bus will run at very low frequency, then
lead to audio playback underrun.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit 3a2a988cc02823297d14aa9001f013adbd15f6e8)
5.4-rM2-2.2.x-imx-squashed
Bai Ping 2017-12-13 13:18:42 +08:00 committed by Dong Aisheng
parent 68449e5c27
commit ac3505d8ee
1 changed files with 29 additions and 25 deletions
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54
drivers/soc/imx/busfreq-imx8mq.c
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@ -114,40 +114,44 @@ static void reduce_bus_freq(void)
* in the future if needed.
*/
if (audio_bus_count) {
clk_prepare_enable(sys1_pll_100m);
if (cur_bus_freq_mode == BUS_FREQ_HIGH) {
clk_prepare_enable(sys1_pll_100m);
update_bus_freq(LOW_BUS_FREQ_100MTS);
update_bus_freq(LOW_BUS_FREQ_100MTS);
/* correct the clock tree info */
clk_disable_unprepare(sys1_pll_100m);
clk_set_parent(dram_alt_src, sys1_pll_100m);
clk_set_parent(dram_core_clk, dram_alt_root);
clk_set_parent(dram_apb_src, sys1_pll_40m);
clk_set_rate(dram_apb_pre_div, 20000000);
/* reduce the NOC & bus clock */
clk_set_rate(noc_div, clk_get_rate(noc_div) / 8);
clk_set_rate(ahb_div, clk_get_rate(ahb_div) / 6);
clk_set_parent(main_axi_src, osc_25m);
/* correct the clock tree info */
clk_disable_unprepare(sys1_pll_100m);
clk_set_parent(dram_alt_src, sys1_pll_100m);
clk_set_parent(dram_core_clk, dram_alt_root);
clk_set_parent(dram_apb_src, sys1_pll_40m);
clk_set_rate(dram_apb_pre_div, 20000000);
/* reduce the NOC & bus clock */
clk_set_rate(noc_div, clk_get_rate(noc_div) / 8);
clk_set_rate(ahb_div, clk_get_rate(ahb_div) / 6);
clk_set_parent(main_axi_src, osc_25m);
}
low_bus_freq_mode = 0;
audio_bus_freq_mode = 1;
cur_bus_freq_mode = BUS_FREQ_AUDIO;
} else {
clk_prepare_enable(sys1_pll_100m);
if (cur_bus_freq_mode == BUS_FREQ_HIGH) {
clk_prepare_enable(sys1_pll_100m);
update_bus_freq(LOW_BUS_FREQ_100MTS);
update_bus_freq(LOW_BUS_FREQ_100MTS);
/* correct the clock tree info */
clk_disable_unprepare(sys1_pll_100m);
clk_set_parent(dram_alt_src, sys1_pll_100m);
clk_set_parent(dram_core_clk, dram_alt_root);
clk_set_parent(dram_apb_src, sys1_pll_40m);
clk_set_rate(dram_apb_pre_div, 20000000);
clk_prepare_enable(sys1_pll_400m);
/* reduce the NOC & bus clock */
clk_set_rate(noc_div, clk_get_rate(noc_div) / 8);
clk_set_rate(ahb_div, clk_get_rate(ahb_div) / 6);
clk_set_parent(main_axi_src, osc_25m);
/* correct the clock tree info */
clk_disable_unprepare(sys1_pll_100m);
clk_set_parent(dram_alt_src, sys1_pll_100m);
clk_set_parent(dram_core_clk, dram_alt_root);
clk_set_parent(dram_apb_src, sys1_pll_40m);
clk_set_rate(dram_apb_pre_div, 20000000);
clk_prepare_enable(sys1_pll_400m);
/* reduce the NOC & bus clock */
clk_set_rate(noc_div, clk_get_rate(noc_div) / 8);
clk_set_rate(ahb_div, clk_get_rate(ahb_div) / 6);
clk_set_parent(main_axi_src, osc_25m);
}
low_bus_freq_mode = 1;
audio_bus_freq_mode = 0;