Revert "staging: tidspbridge - remove custom mmu code from tiomap3430.c"
This reverts commit e7396e77d9.
Signed-off-by: Felipe Contreras <felipe.contreras@gmail.com>
Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
hifive-unleashed-5.1
Felipe Contreras
Omar Ramirez Luna
parent
6c4c899ee2
commit
ac8a139a14
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@ -330,6 +330,7 @@ struct bridge_dev_context {
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*/
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u32 dw_dsp_ext_base_addr; /* See the comment above */
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u32 dw_api_reg_base; /* API mem map'd registers */
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void __iomem *dw_dsp_mmu_base; /* DSP MMU Mapped registers */
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u32 dw_api_clk_base; /* CLK Registers */
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u32 dw_dsp_clk_m2_base; /* DSP Clock Module m2 */
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u32 dw_public_rhea; /* Pub Rhea */
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@ -355,6 +356,7 @@ struct bridge_dev_context {
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/* TC Settings */
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bool tc_word_swap_on; /* Traffic Controller Word Swap */
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struct pg_table_attrs *pt_attrs;
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u32 dsp_per_clks;
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};
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@ -116,8 +116,56 @@ static int bridge_dev_create(struct bridge_dev_context
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static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
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u32 dw_cmd, void *pargs);
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static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt);
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static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa,
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u32 va, u32 size,
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struct hw_mmu_map_attrs_t *map_attrs);
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static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
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u32 size, struct hw_mmu_map_attrs_t *attrs);
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static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
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u32 ul_mpu_addr, u32 virt_addr,
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u32 ul_num_bytes,
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struct hw_mmu_map_attrs_t *hw_attrs);
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bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr);
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/* ----------------------------------- Globals */
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/* Attributes of L2 page tables for DSP MMU */
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struct page_info {
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u32 num_entries; /* Number of valid PTEs in the L2 PT */
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};
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/* Attributes used to manage the DSP MMU page tables */
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struct pg_table_attrs {
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spinlock_t pg_lock; /* Critical section object handle */
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u32 l1_base_pa; /* Physical address of the L1 PT */
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u32 l1_base_va; /* Virtual address of the L1 PT */
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u32 l1_size; /* Size of the L1 PT */
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u32 l1_tbl_alloc_pa;
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/* Physical address of Allocated mem for L1 table. May not be aligned */
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u32 l1_tbl_alloc_va;
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/* Virtual address of Allocated mem for L1 table. May not be aligned */
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u32 l1_tbl_alloc_sz;
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/* Size of consistent memory allocated for L1 table.
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* May not be aligned */
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u32 l2_base_pa; /* Physical address of the L2 PT */
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u32 l2_base_va; /* Virtual address of the L2 PT */
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u32 l2_size; /* Size of the L2 PT */
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u32 l2_tbl_alloc_pa;
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/* Physical address of Allocated mem for L2 table. May not be aligned */
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u32 l2_tbl_alloc_va;
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/* Virtual address of Allocated mem for L2 table. May not be aligned */
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u32 l2_tbl_alloc_sz;
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/* Size of consistent memory allocated for L2 table.
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* May not be aligned */
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u32 l2_num_pages; /* Number of allocated L2 PT */
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/* Array [l2_num_pages] of L2 PT info structs */
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struct page_info *pg_info;
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};
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/*
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* This Bridge driver's function interface table.
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*/
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@ -166,6 +214,27 @@ static struct bridge_drv_interface drv_interface_fxns = {
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bridge_msg_set_queue_id,
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};
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static inline void flush_all(struct bridge_dev_context *dev_context)
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{
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if (dev_context->dw_brd_state == BRD_DSP_HIBERNATION ||
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dev_context->dw_brd_state == BRD_HIBERNATION)
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wake_dsp(dev_context, NULL);
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hw_mmu_tlb_flush_all(dev_context->dw_dsp_mmu_base);
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}
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static void bad_page_dump(u32 pa, struct page *pg)
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{
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pr_emerg("DSPBRIDGE: MAP function: COUNT 0 FOR PA 0x%x\n", pa);
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pr_emerg("Bad page state in process '%s'\n"
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"page:%p flags:0x%0*lx mapping:%p mapcount:%d count:%d\n"
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"Backtrace:\n",
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current->comm, pg, (int)(2 * sizeof(unsigned long)),
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(unsigned long)pg->flags, pg->mapping,
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page_mapcount(pg), page_count(pg));
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dump_stack();
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}
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/*
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* ======== bridge_drv_entry ========
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* purpose:
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@ -571,6 +640,7 @@ static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt)
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{
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int status = 0;
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struct bridge_dev_context *dev_context = dev_ctxt;
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struct pg_table_attrs *pt_attrs;
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u32 dsp_pwr_state;
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int i;
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struct bridge_ioctl_extproc *tlb = dev_context->atlb_entry;
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@ -609,6 +679,14 @@ static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt)
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dsp_wdt_enable(false);
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/* This is a good place to clear the MMU page tables as well */
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if (dev_context->pt_attrs) {
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pt_attrs = dev_context->pt_attrs;
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memset((u8 *) pt_attrs->l1_base_va, 0x00, pt_attrs->l1_size);
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memset((u8 *) pt_attrs->l2_base_va, 0x00, pt_attrs->l2_size);
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memset((u8 *) pt_attrs->pg_info, 0x00,
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(pt_attrs->l2_num_pages * sizeof(struct page_info)));
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}
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/* Reset DSP */
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(*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
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OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
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@ -699,6 +777,10 @@ static int bridge_dev_create(struct bridge_dev_context
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struct bridge_dev_context *dev_context = NULL;
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s32 entry_ndx;
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struct cfg_hostres *resources = config_param;
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struct pg_table_attrs *pt_attrs;
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u32 pg_tbl_pa;
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u32 pg_tbl_va;
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u32 align_size;
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struct drv_data *drv_datap = dev_get_drvdata(bridge);
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/* Allocate and initialize a data structure to contain the bridge driver
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@ -729,8 +811,97 @@ static int bridge_dev_create(struct bridge_dev_context
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if (!dev_context->dw_dsp_base_addr)
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status = -EPERM;
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pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL);
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if (pt_attrs != NULL) {
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/* Assuming that we use only DSP's memory map
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* until 0x4000:0000 , we would need only 1024
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* L1 enties i.e L1 size = 4K */
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pt_attrs->l1_size = 0x1000;
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align_size = pt_attrs->l1_size;
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/* Align sizes are expected to be power of 2 */
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/* we like to get aligned on L1 table size */
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pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l1_size,
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align_size, &pg_tbl_pa);
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/* Check if the PA is aligned for us */
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if ((pg_tbl_pa) & (align_size - 1)) {
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/* PA not aligned to page table size ,
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* try with more allocation and align */
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mem_free_phys_mem((void *)pg_tbl_va, pg_tbl_pa,
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pt_attrs->l1_size);
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/* we like to get aligned on L1 table size */
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pg_tbl_va =
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(u32) mem_alloc_phys_mem((pt_attrs->l1_size) * 2,
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align_size, &pg_tbl_pa);
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/* We should be able to get aligned table now */
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pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
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pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
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pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size * 2;
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/* Align the PA to the next 'align' boundary */
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pt_attrs->l1_base_pa =
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((pg_tbl_pa) +
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(align_size - 1)) & (~(align_size - 1));
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pt_attrs->l1_base_va =
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pg_tbl_va + (pt_attrs->l1_base_pa - pg_tbl_pa);
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} else {
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/* We got aligned PA, cool */
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pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
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pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
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pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size;
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pt_attrs->l1_base_pa = pg_tbl_pa;
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pt_attrs->l1_base_va = pg_tbl_va;
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}
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if (pt_attrs->l1_base_va)
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memset((u8 *) pt_attrs->l1_base_va, 0x00,
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pt_attrs->l1_size);
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/* number of L2 page tables = DMM pool used + SHMMEM +EXTMEM +
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* L4 pages */
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pt_attrs->l2_num_pages = ((DMMPOOLSIZE >> 20) + 6);
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pt_attrs->l2_size = HW_MMU_COARSE_PAGE_SIZE *
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pt_attrs->l2_num_pages;
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align_size = 4; /* Make it u32 aligned */
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/* we like to get aligned on L1 table size */
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pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l2_size,
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align_size, &pg_tbl_pa);
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pt_attrs->l2_tbl_alloc_pa = pg_tbl_pa;
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pt_attrs->l2_tbl_alloc_va = pg_tbl_va;
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pt_attrs->l2_tbl_alloc_sz = pt_attrs->l2_size;
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pt_attrs->l2_base_pa = pg_tbl_pa;
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pt_attrs->l2_base_va = pg_tbl_va;
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if (pt_attrs->l2_base_va)
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memset((u8 *) pt_attrs->l2_base_va, 0x00,
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pt_attrs->l2_size);
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pt_attrs->pg_info = kzalloc(pt_attrs->l2_num_pages *
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sizeof(struct page_info), GFP_KERNEL);
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dev_dbg(bridge,
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"L1 pa %x, va %x, size %x\n L2 pa %x, va "
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"%x, size %x\n", pt_attrs->l1_base_pa,
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pt_attrs->l1_base_va, pt_attrs->l1_size,
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pt_attrs->l2_base_pa, pt_attrs->l2_base_va,
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pt_attrs->l2_size);
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dev_dbg(bridge, "pt_attrs %p L2 NumPages %x pg_info %p\n",
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pt_attrs, pt_attrs->l2_num_pages, pt_attrs->pg_info);
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}
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if ((pt_attrs != NULL) && (pt_attrs->l1_base_va != 0) &&
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(pt_attrs->l2_base_va != 0) && (pt_attrs->pg_info != NULL))
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dev_context->pt_attrs = pt_attrs;
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else
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status = -ENOMEM;
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if (!status) {
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spin_lock_init(&pt_attrs->pg_lock);
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dev_context->tc_word_swap_on = drv_datap->tc_wordswapon;
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/* Set the Clock Divisor for the DSP module */
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udelay(5);
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/* MMU address is obtained from the host
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* resources struct */
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dev_context->dw_dsp_mmu_base = resources->dw_dmmu_base;
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}
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if (!status) {
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dev_context->hdev_obj = hdev_obj;
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/* Store current board state. */
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dev_context->dw_brd_state = BRD_UNKNOWN;
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@ -740,6 +911,23 @@ static int bridge_dev_create(struct bridge_dev_context
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/* Return ptr to our device state to the DSP API for storage */
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*dev_cntxt = dev_context;
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} else {
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if (pt_attrs != NULL) {
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kfree(pt_attrs->pg_info);
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if (pt_attrs->l2_tbl_alloc_va) {
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mem_free_phys_mem((void *)
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pt_attrs->l2_tbl_alloc_va,
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pt_attrs->l2_tbl_alloc_pa,
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pt_attrs->l2_tbl_alloc_sz);
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}
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if (pt_attrs->l1_tbl_alloc_va) {
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mem_free_phys_mem((void *)
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pt_attrs->l1_tbl_alloc_va,
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pt_attrs->l1_tbl_alloc_pa,
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pt_attrs->l1_tbl_alloc_sz);
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}
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}
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kfree(pt_attrs);
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kfree(dev_context);
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}
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func_end:
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@ -807,6 +995,7 @@ static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
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*/
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static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt)
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{
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struct pg_table_attrs *pt_attrs;
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int status = 0;
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struct bridge_dev_context *dev_context = (struct bridge_dev_context *)
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dev_ctxt;
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@ -820,6 +1009,23 @@ static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt)
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/* first put the device to stop state */
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bridge_brd_stop(dev_context);
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if (dev_context->pt_attrs) {
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pt_attrs = dev_context->pt_attrs;
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kfree(pt_attrs->pg_info);
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if (pt_attrs->l2_tbl_alloc_va) {
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mem_free_phys_mem((void *)pt_attrs->l2_tbl_alloc_va,
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pt_attrs->l2_tbl_alloc_pa,
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pt_attrs->l2_tbl_alloc_sz);
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}
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if (pt_attrs->l1_tbl_alloc_va) {
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mem_free_phys_mem((void *)pt_attrs->l1_tbl_alloc_va,
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pt_attrs->l1_tbl_alloc_pa,
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pt_attrs->l1_tbl_alloc_sz);
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}
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kfree(pt_attrs);
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}
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if (dev_context->resources) {
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host_res = dev_context->resources;
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@ -1115,6 +1321,225 @@ int user_to_dsp_unmap(struct iommu *mmu, u32 da)
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return 0;
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}
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/*
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* ======== pte_update ========
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* This function calculates the optimum page-aligned addresses and sizes
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* Caller must pass page-aligned values
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*/
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static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa,
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u32 va, u32 size,
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struct hw_mmu_map_attrs_t *map_attrs)
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{
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u32 i;
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u32 all_bits;
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u32 pa_curr = pa;
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u32 va_curr = va;
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u32 num_bytes = size;
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struct bridge_dev_context *dev_context = dev_ctxt;
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int status = 0;
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u32 page_size[] = { HW_PAGE_SIZE16MB, HW_PAGE_SIZE1MB,
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HW_PAGE_SIZE64KB, HW_PAGE_SIZE4KB
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};
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while (num_bytes && !status) {
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/* To find the max. page size with which both PA & VA are
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* aligned */
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all_bits = pa_curr | va_curr;
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for (i = 0; i < 4; i++) {
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if ((num_bytes >= page_size[i]) && ((all_bits &
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(page_size[i] -
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1)) == 0)) {
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status =
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pte_set(dev_context->pt_attrs, pa_curr,
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va_curr, page_size[i], map_attrs);
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pa_curr += page_size[i];
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va_curr += page_size[i];
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num_bytes -= page_size[i];
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/* Don't try smaller sizes. Hopefully we have
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* reached an address aligned to a bigger page
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* size */
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break;
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}
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}
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}
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return status;
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}
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/*
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* ======== pte_set ========
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* This function calculates PTE address (MPU virtual) to be updated
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* It also manages the L2 page tables
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*/
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static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
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u32 size, struct hw_mmu_map_attrs_t *attrs)
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{
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u32 i;
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u32 pte_val;
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u32 pte_addr_l1;
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u32 pte_size;
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/* Base address of the PT that will be updated */
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u32 pg_tbl_va;
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u32 l1_base_va;
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/* Compiler warns that the next three variables might be used
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* uninitialized in this function. Doesn't seem so. Working around,
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* anyways. */
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u32 l2_base_va = 0;
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u32 l2_base_pa = 0;
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u32 l2_page_num = 0;
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int status = 0;
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l1_base_va = pt->l1_base_va;
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pg_tbl_va = l1_base_va;
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if ((size == HW_PAGE_SIZE64KB) || (size == HW_PAGE_SIZE4KB)) {
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/* Find whether the L1 PTE points to a valid L2 PT */
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pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va);
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if (pte_addr_l1 <= (pt->l1_base_va + pt->l1_size)) {
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pte_val = *(u32 *) pte_addr_l1;
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pte_size = hw_mmu_pte_size_l1(pte_val);
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} else {
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return -EPERM;
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}
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spin_lock(&pt->pg_lock);
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if (pte_size == HW_MMU_COARSE_PAGE_SIZE) {
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/* Get the L2 PA from the L1 PTE, and find
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* corresponding L2 VA */
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l2_base_pa = hw_mmu_pte_coarse_l1(pte_val);
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l2_base_va =
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l2_base_pa - pt->l2_base_pa + pt->l2_base_va;
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l2_page_num =
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(l2_base_pa -
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pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE;
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} else if (pte_size == 0) {
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/* L1 PTE is invalid. Allocate a L2 PT and
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* point the L1 PTE to it */
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/* Find a free L2 PT. */
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for (i = 0; (i < pt->l2_num_pages) &&
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(pt->pg_info[i].num_entries != 0); i++)
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;;
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if (i < pt->l2_num_pages) {
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l2_page_num = i;
|
||||
l2_base_pa = pt->l2_base_pa + (l2_page_num *
|
||||
HW_MMU_COARSE_PAGE_SIZE);
|
||||
l2_base_va = pt->l2_base_va + (l2_page_num *
|
||||
HW_MMU_COARSE_PAGE_SIZE);
|
||||
/* Endianness attributes are ignored for
|
||||
* HW_MMU_COARSE_PAGE_SIZE */
|
||||
status =
|
||||
hw_mmu_pte_set(l1_base_va, l2_base_pa, va,
|
||||
HW_MMU_COARSE_PAGE_SIZE,
|
||||
attrs);
|
||||
} else {
|
||||
status = -ENOMEM;
|
||||
}
|
||||
} else {
|
||||
/* Found valid L1 PTE of another size.
|
||||
* Should not overwrite it. */
|
||||
status = -EPERM;
|
||||
}
|
||||
if (!status) {
|
||||
pg_tbl_va = l2_base_va;
|
||||
if (size == HW_PAGE_SIZE64KB)
|
||||
pt->pg_info[l2_page_num].num_entries += 16;
|
||||
else
|
||||
pt->pg_info[l2_page_num].num_entries++;
|
||||
dev_dbg(bridge, "PTE: L2 BaseVa %x, BasePa %x, PageNum "
|
||||
"%x, num_entries %x\n", l2_base_va,
|
||||
l2_base_pa, l2_page_num,
|
||||
pt->pg_info[l2_page_num].num_entries);
|
||||
}
|
||||
spin_unlock(&pt->pg_lock);
|
||||
}
|
||||
if (!status) {
|
||||
dev_dbg(bridge, "PTE: pg_tbl_va %x, pa %x, va %x, size %x\n",
|
||||
pg_tbl_va, pa, va, size);
|
||||
dev_dbg(bridge, "PTE: endianism %x, element_size %x, "
|
||||
"mixed_size %x\n", attrs->endianism,
|
||||
attrs->element_size, attrs->mixed_size);
|
||||
status = hw_mmu_pte_set(pg_tbl_va, pa, va, size, attrs);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Memory map kernel VA -- memory allocated with vmalloc */
|
||||
static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
|
||||
u32 ul_mpu_addr, u32 virt_addr,
|
||||
u32 ul_num_bytes,
|
||||
struct hw_mmu_map_attrs_t *hw_attrs)
|
||||
{
|
||||
int status = 0;
|
||||
struct page *page[1];
|
||||
u32 i;
|
||||
u32 pa_curr;
|
||||
u32 pa_next;
|
||||
u32 va_curr;
|
||||
u32 size_curr;
|
||||
u32 num_pages;
|
||||
u32 pa;
|
||||
u32 num_of4k_pages;
|
||||
u32 temp = 0;
|
||||
|
||||
/*
|
||||
* Do Kernel va to pa translation.
|
||||
* Combine physically contiguous regions to reduce TLBs.
|
||||
* Pass the translated pa to pte_update.
|
||||
*/
|
||||
num_pages = ul_num_bytes / PAGE_SIZE; /* PAGE_SIZE = OS page size */
|
||||
i = 0;
|
||||
va_curr = ul_mpu_addr;
|
||||
page[0] = vmalloc_to_page((void *)va_curr);
|
||||
pa_next = page_to_phys(page[0]);
|
||||
while (!status && (i < num_pages)) {
|
||||
/*
|
||||
* Reuse pa_next from the previous iteraion to avoid
|
||||
* an extra va2pa call
|
||||
*/
|
||||
pa_curr = pa_next;
|
||||
size_curr = PAGE_SIZE;
|
||||
/*
|
||||
* If the next page is physically contiguous,
|
||||
* map it with the current one by increasing
|
||||
* the size of the region to be mapped
|
||||
*/
|
||||
while (++i < num_pages) {
|
||||
page[0] =
|
||||
vmalloc_to_page((void *)(va_curr + size_curr));
|
||||
pa_next = page_to_phys(page[0]);
|
||||
|
||||
if (pa_next == (pa_curr + size_curr))
|
||||
size_curr += PAGE_SIZE;
|
||||
else
|
||||
break;
|
||||
|
||||
}
|
||||
if (pa_next == 0) {
|
||||
status = -ENOMEM;
|
||||
break;
|
||||
}
|
||||
pa = pa_curr;
|
||||
num_of4k_pages = size_curr / HW_PAGE_SIZE4KB;
|
||||
while (temp++ < num_of4k_pages) {
|
||||
get_page(PHYS_TO_PAGE(pa));
|
||||
pa += HW_PAGE_SIZE4KB;
|
||||
}
|
||||
status = pte_update(dev_context, pa_curr, virt_addr +
|
||||
(va_curr - ul_mpu_addr), size_curr,
|
||||
hw_attrs);
|
||||
va_curr += size_curr;
|
||||
}
|
||||
/*
|
||||
* In any case, flush the TLB
|
||||
* This is called from here instead from pte_update to avoid unnecessary
|
||||
* repetition while mapping non-contiguous physical regions of a virtual
|
||||
* region
|
||||
*/
|
||||
flush_all(dev_context);
|
||||
dev_dbg(bridge, "%s status %x\n", __func__, status);
|
||||
return status;
|
||||
}
|
||||
|
||||
/*
|
||||
* ======== wait_for_start ========
|
||||
* Wait for the singal from DSP that it has started, or time out.
|
||||
|
|
|
|||
Loading…
Reference in New Issue