drm/radeon/kms: improve pflip precision on r1xx-r4xx
The update pending bit has a separate enable bit. Cc: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -76,6 +76,8 @@ void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
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/* make sure flip is at vb rather than hb */
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tmp = RREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset);
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tmp &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
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/* make sure pending bit is asserted */
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tmp |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
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WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, tmp);
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/* set pageflip to happen as late as possible in the vblank interval.
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@ -104,9 +106,9 @@ u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
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/* update the scanout addresses */
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WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
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/* Note: We don't wait for update_pending to assert, as this never
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* happens for some reason on R1xx - R4xx. Adds a bit of imprecision.
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*/
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/* Wait for update_pending to go high. */
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while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET));
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DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
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/* Unlock the lock, so double-buffering can take place inside vblank */
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tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
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@ -510,6 +510,8 @@
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# define RADEON_CRTC_TILE_EN (1 << 15)
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# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
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# define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)
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# define RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN (1 << 28)
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# define RADEON_CRTC_GUI_TRIG_OFFSET_RIGHT_EN (1 << 29)
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#define R300_CRTC_TILE_X0_Y0 0x0350
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#define R300_CRTC2_TILE_X0_Y0 0x0358
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