[POWERPC] 4xx: Add 440SPe revA runtime detection to PCIe
This patch adds runtime detection of the 440SPe revision A chips. These chips are equipped with a slighly different PCIe core and need special/ different initialization. The compatible node is changed to "plb-pciex-440spe" ("A" and "B" dropped). This is needed for boards that can be equipped with both PPC revisions like the AMCC Yucca. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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@ -267,7 +267,7 @@
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex";
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compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
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primary;
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port = <0>; /* port number */
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reg = <d 00000000 20000000 /* Config space access */
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@ -308,7 +308,7 @@
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex";
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compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
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primary;
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port = <1>; /* port number */
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reg = <d 20000000 20000000 /* Config space access */
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@ -349,7 +349,7 @@
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex";
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compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
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primary;
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port = <2>; /* port number */
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reg = <d 40000000 20000000 /* Config space access */
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@ -49,6 +49,15 @@ extern unsigned long total_memory;
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#define RES_TO_U32_HIGH(val) (0)
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#endif
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static inline int ppc440spe_revA(void)
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{
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/* Catch both 440SPe variants, with and without RAID6 support */
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if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)
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return 1;
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else
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return 0;
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}
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static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
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{
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struct pci_controller *hose;
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@ -516,8 +525,7 @@ static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
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*
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* We support 3 parts currently based on the compatible property:
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*
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* ibm,plb-pciex-440speA
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* ibm,plb-pciex-440speB
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* ibm,plb-pciex-440spe
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* ibm,plb-pciex-405ex
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*
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* Anything else will be rejected for now as they are all subtly
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@ -688,7 +696,7 @@ static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
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mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
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mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
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if (of_device_is_compatible(port->node, "ibm,plb-pciex-440speA"))
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if (ppc440spe_revA())
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mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
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mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
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mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
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@ -767,7 +775,6 @@ static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
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.setup_utl = ppc440speB_pciex_init_utl,
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};
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#endif /* CONFIG_44x */
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#ifdef CONFIG_40x
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@ -881,10 +888,12 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
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return 0;
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#ifdef CONFIG_44x
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if (of_device_is_compatible(np, "ibm,plb-pciex-440speA"))
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ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
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else if (of_device_is_compatible(np, "ibm,plb-pciex-440speB"))
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ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
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if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {
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if (ppc440spe_revA())
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ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
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else
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ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
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}
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#endif /* CONFIG_44x */
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#ifdef CONFIG_40x
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if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
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