powerpc/85xx: mpc85xxcds - Fix PCI I/O space resource of PCI bridge
There is a PCI bridge(Tsi310) between the MPC8548 and a VIA southbridge chip. The bootloader sets the PCI bridge to open a window from 0x0000 to 0x1fff on the PCI I/O space. But the kernel can't set the I/O resource. In the routine pci_read_bridge_io(), if the base which is read from PCI_IO_BASE is equal to zero, the routine don't set the I/O resource of the child bus. To allow the legacy I/O space on the VIA southbridge to be accessed, use the fixup to fix the PCI I/O space of the PCI bridge. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -3,7 +3,7 @@
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*
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*
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* Maintained by Kumar Gala (see MAINTAINERS for contact information)
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* Maintained by Kumar Gala (see MAINTAINERS for contact information)
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*
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*
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* Copyright 2005 Freescale Semiconductor Inc.
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* Copyright 2005, 2011-2012 Freescale Semiconductor Inc.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* under the terms of the GNU General Public License as published by the
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@ -158,6 +158,33 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
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DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
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DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
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DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
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DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
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#define PCI_DEVICE_ID_IDT_TSI310 0x01a7
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/*
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* Fix Tsi310 PCI-X bridge resource.
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* Force the bridge to open a window from 0x0000-0x1fff in PCI I/O space.
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* This allows legacy I/O(i8259, etc) on the VIA southbridge to be accessed.
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*/
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void mpc85xx_cds_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev = bus->self;
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struct resource *res = bus->resource[0];
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if (dev != NULL &&
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dev->vendor == PCI_VENDOR_ID_IBM &&
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dev->device == PCI_DEVICE_ID_IDT_TSI310) {
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if (res) {
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res->start = 0;
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res->end = 0x1fff;
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res->flags = IORESOURCE_IO;
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pr_info("mpc85xx_cds: PCI bridge resource fixup applied\n");
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pr_info("mpc85xx_cds: %pR\n", res);
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}
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}
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fsl_pcibios_fixup_bus(bus);
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}
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#ifdef CONFIG_PPC_I8259
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#ifdef CONFIG_PPC_I8259
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static void mpc85xx_8259_cascade_handler(unsigned int irq,
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static void mpc85xx_8259_cascade_handler(unsigned int irq,
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struct irq_desc *desc)
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struct irq_desc *desc)
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@ -322,7 +349,7 @@ define_machine(mpc85xx_cds) {
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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#ifdef CONFIG_PCI
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#ifdef CONFIG_PCI
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.restart = mpc85xx_cds_restart,
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.restart = mpc85xx_cds_restart,
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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.pcibios_fixup_bus = mpc85xx_cds_fixup_bus,
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#else
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#else
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.restart = fsl_rstcr_restart,
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.restart = fsl_rstcr_restart,
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#endif
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#endif
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