bnx2x: New init infrastructure
This new initialization code supports the 57711 HW. It also supports the emulation and FPGA for the 57711 and 57710 initializations values (very small amount of code which is very helpful in the lab - less than 30 lines). The initialization is done via DMAE after the DMAE block is ready - before it is ready, some of the initialization is done via PCI configuration transactions (referred to as indirect write). A mutex to protect the DMAE from being overlapped was added. There are few new registers which needs to be initialized by SW - the full comment for those registers is added to the register file. A place holder for the 57711 (referred to as E1H) microcode was added- the microcode itself is too big and it is split over the following 4 patches Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
Eilon Greenstein
David S. Miller
parent
c18487ee24
commit
ad8d394804
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@ -557,25 +557,37 @@ struct bnx2x {
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u32 shmem_base;
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u32 chip_id;
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u32 chip_id;
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/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
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#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
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#define CHIP_ID(bp) (bp->chip_id & 0xfffffff0)
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#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
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#define CHIP_NUM(bp) (bp->chip_id >> 16)
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#define CHIP_NUM_57710 0x164e
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#define CHIP_NUM_57711 0x164f
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#define CHIP_NUM_57711E 0x1650
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#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
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#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
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#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
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#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
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CHIP_IS_57711E(bp))
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#define IS_E1H_OFFSET CHIP_IS_E1H(bp)
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#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
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#define CHIP_REV_Ax 0x00000000
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#define CHIP_REV_Bx 0x00001000
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#define CHIP_REV_Cx 0x00002000
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#define CHIP_REV_EMUL 0x0000e000
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#define CHIP_REV_FPGA 0x0000f000
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#define CHIP_REV_IS_SLOW(bp) ((CHIP_REV(bp) == CHIP_REV_EMUL) || \
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(CHIP_REV(bp) == CHIP_REV_FPGA))
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#define CHIP_REV_IS_EMUL(bp) (CHIP_REV(bp) == CHIP_REV_EMUL)
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#define CHIP_REV_IS_FPGA(bp) (CHIP_REV(bp) == CHIP_REV_FPGA)
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#define CHIP_REV(bp) (bp->chip_id & 0x0000f000)
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#define CHIP_REV_Ax 0x00000000
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/* assume maximum 5 revisions */
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#define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
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/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
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#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
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!(CHIP_REV(bp) & 0x00001000))
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/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
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#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
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(CHIP_REV(bp) & 0x00001000))
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#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
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#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0x0000000f)
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#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
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((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
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#define CHIP_METAL(bp) (bp->chip_id & 0x00000ff0)
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#define CHIP_BOND_ID(bp) (bp->chip_id & 0x0000000f)
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u16 fw_seq;
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u16 fw_drv_pulse_wr_seq;
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@ -678,6 +690,13 @@ struct bnx2x {
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struct dmae_command dmae;
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int executer_idx;
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int dmae_ready;
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/* used to synchronize dmae accesses */
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struct mutex dmae_mutex;
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struct dmae_command init_dmae;
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u32 old_brb_discard;
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struct bmac_stats old_bmac;
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struct tstorm_per_client_stats old_tclient;
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@ -685,7 +704,7 @@ struct bnx2x {
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void *gunzip_buf;
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dma_addr_t gunzip_mapping;
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int gunzip_outlen;
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#define FW_BUF_SIZE 0x8000
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#define FW_BUF_SIZE 0x8000
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};
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@ -774,12 +793,6 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
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#define STROM_ASSERT_ARRAY_SIZE 50
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#define MDIO_INDIRECT_REG_ADDR 0x1f
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#define MDIO_SET_REG_BANK(bp, reg_bank) \
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bnx2x_mdio22_write(bp, MDIO_INDIRECT_REG_ADDR, reg_bank)
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#define MDIO_ACCESS_TIMEOUT 1000
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/* must be used on a CID before placing it on a HW ring */
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#define HW_CID(bp, x) (x | (bp->port << 23))
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@ -818,6 +831,42 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
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DPM_TRIGER_TYPE); \
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} while (0)
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/* DMAE command defines */
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#define DMAE_CMD_SRC_PCI 0
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#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
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#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
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#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
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#define DMAE_CMD_C_DST_PCI 0
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#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
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#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
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#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
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#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
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#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
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#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
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#define DMAE_CMD_PORT_0 0
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#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
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#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
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#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
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#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
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#define DMAE_LEN32_RD_MAX 0x80
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#define DMAE_LEN32_WR_MAX 0x400
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#define DMAE_COMP_VAL 0xe0d0d0ae
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#define MAX_DMAE_C_PER_PORT 8
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#define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
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BP_E1HVN(bp))
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#define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
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E1HVN_MAX)
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/* PCIE link and speed */
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#define PCICFG_LINK_WIDTH 0x1f00000
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#define PCICFG_LINK_WIDTH_SHIFT 20
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@ -522,8 +522,21 @@ struct dev_info { /* size */
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#define FUNC_0 0
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#define FUNC_1 1
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#define FUNC_2 2
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#define FUNC_3 3
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#define FUNC_4 4
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#define FUNC_5 5
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#define FUNC_6 6
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#define FUNC_7 7
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#define E1_FUNC_MAX 2
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#define FUNC_MAX E1_FUNC_MAX
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#define E1H_FUNC_MAX 8
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#define VN_0 0
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#define VN_1 1
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#define VN_2 2
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#define VN_3 3
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#define E1VN_MAX 1
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#define E1HVN_MAX 4
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/* This value (in milliseconds) determines the frequency of the driver
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@ -747,7 +760,11 @@ struct shmem_region { /* SharedMem Offset (size) */
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struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
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struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
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struct drv_func_mb func_mb[FUNC_MAX]; /* 0x684 (44*2=0x58) */
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#if defined(b710)
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struct drv_func_mb func_mb[E1_FUNC_MAX]; /* 0x684 (44*2=0x58) */
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#else
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struct drv_func_mb func_mb[E1H_FUNC_MAX];
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#endif
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}; /* 0x6dc */
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@ -901,8 +918,10 @@ struct dmae_command {
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#define DMAE_COMMAND_SRC_RESET_SHIFT 13
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#define DMAE_COMMAND_DST_RESET (0x1<<14)
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#define DMAE_COMMAND_DST_RESET_SHIFT 14
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#define DMAE_COMMAND_RESERVED0 (0x1FFFF<<15)
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#define DMAE_COMMAND_RESERVED0_SHIFT 15
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#define DMAE_COMMAND_E1HVN (0x3<<15)
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#define DMAE_COMMAND_E1HVN_SHIFT 15
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#define DMAE_COMMAND_RESERVED0 (0x7FFF<<17)
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#define DMAE_COMMAND_RESERVED0_SHIFT 17
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u32 src_addr_lo;
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u32 src_addr_hi;
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u32 dst_addr_lo;
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@ -22,7 +22,8 @@
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#define INIT_ASIC 0x4
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#define INIT_HARDWARE 0x7
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#define STORM_INTMEM_SIZE (0x5800 / 4)
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#define STORM_INTMEM_SIZE_E1 (0x5800 / 4)
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#define STORM_INTMEM_SIZE_E1H (0x10000 / 4)
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#define TSTORM_INTMEM_ADDR 0x1a0000
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#define CSTORM_INTMEM_ADDR 0x220000
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#define XSTORM_INTMEM_ADDR 0x2a0000
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@ -30,7 +31,7 @@
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/* Init operation types and structures */
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/* Common for both E1 and E1H */
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#define OP_RD 0x1 /* read single register */
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#define OP_WR 0x2 /* write single register */
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#define OP_IW 0x3 /* write single register using mailbox */
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@ -38,7 +39,37 @@
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#define OP_SI 0x5 /* copy a string using mailbox */
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#define OP_ZR 0x6 /* clear memory */
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#define OP_ZP 0x7 /* unzip then copy with DMAE */
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#define OP_WB 0x8 /* copy a string using DMAE */
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#define OP_WR_64 0x8 /* write 64 bit pattern */
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#define OP_WB 0x9 /* copy a string using DMAE */
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/* Operation specific for E1 */
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#define OP_RD_E1 0xa /* read single register */
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#define OP_WR_E1 0xb /* write single register */
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#define OP_IW_E1 0xc /* write single register using mailbox */
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#define OP_SW_E1 0xd /* copy a string to the device */
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#define OP_SI_E1 0xe /* copy a string using mailbox */
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#define OP_ZR_E1 0xf /* clear memory */
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#define OP_ZP_E1 0x10 /* unzip then copy with DMAE */
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#define OP_WR_64_E1 0x11 /* write 64 bit pattern on E1 */
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#define OP_WB_E1 0x12 /* copy a string using DMAE */
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/* Operation specific for E1H */
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#define OP_RD_E1H 0x13 /* read single register */
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#define OP_WR_E1H 0x14 /* write single register */
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#define OP_IW_E1H 0x15 /* write single register using mailbox */
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#define OP_SW_E1H 0x16 /* copy a string to the device */
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#define OP_SI_E1H 0x17 /* copy a string using mailbox */
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#define OP_ZR_E1H 0x18 /* clear memory */
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#define OP_ZP_E1H 0x19 /* unzip then copy with DMAE */
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#define OP_WR_64_E1H 0x1a /* write 64 bit pattern on E1H */
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#define OP_WB_E1H 0x1b /* copy a string using DMAE */
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/* FPGA and EMUL specific operations */
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#define OP_WR_EMUL_E1H 0x1c /* write single register on E1H Emul */
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#define OP_WR_EMUL 0x1d /* write single register on Emulation */
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#define OP_WR_FPGA 0x1e /* write single register on FPGA */
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#define OP_WR_ASIC 0x1f /* write single register on ASIC */
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struct raw_op {
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u32 op :8;
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@ -117,11 +148,117 @@ static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
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}
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}
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static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len)
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{
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#ifdef USE_DMAE
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int offset = 0;
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if (bp->dmae_ready) {
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while (len > DMAE_LEN32_WR_MAX) {
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bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
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addr + offset, DMAE_LEN32_WR_MAX);
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offset += DMAE_LEN32_WR_MAX * 4;
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len -= DMAE_LEN32_WR_MAX;
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}
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bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
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addr + offset, len);
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} else
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bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
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#else
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bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
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#endif
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}
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static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
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{
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if ((len * 4) > FW_BUF_SIZE) {
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BNX2X_ERR("LARGE DMAE OPERATION ! addr 0x%x len 0x%x\n",
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addr, len*4);
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return;
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}
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memset(bp->gunzip_buf, fill, len * 4);
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bnx2x_write_big_buf(bp, addr, len);
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}
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static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
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u32 len64)
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{
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u32 buf_len32 = FW_BUF_SIZE/4;
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u32 len = len64*2;
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u64 data64 = 0;
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int i;
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/* 64 bit value is in a blob: first low DWORD, then high DWORD */
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data64 = HILO_U64((*(data + 1)), (*data));
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len64 = min((u32)(FW_BUF_SIZE/8), len64);
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for (i = 0; i < len64; i++) {
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u64 *pdata = ((u64 *)(bp->gunzip_buf)) + i;
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*pdata = data64;
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}
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for (i = 0; i < len; i += buf_len32) {
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u32 cur_len = min(buf_len32, len - i);
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bnx2x_write_big_buf(bp, addr + i * 4, cur_len);
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}
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}
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/*********************************************************
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There are different blobs for each PRAM section.
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In addition, each blob write operation is divided into a few operations
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in order to decrease the amount of phys. contigious buffer needed.
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Thus, when we select a blob the address may be with some offset
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from the beginning of PRAM section.
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The same holds for the INT_TABLE sections.
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**********************************************************/
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#define IF_IS_INT_TABLE_ADDR(base, addr) \
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if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
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#define IF_IS_PRAM_ADDR(base, addr) \
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if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
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static const u32 *bnx2x_sel_blob(u32 addr, const u32 *data, int is_e1)
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{
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IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
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data = is_e1 ? tsem_int_table_data_e1 :
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tsem_int_table_data_e1h;
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else
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IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
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data = is_e1 ? csem_int_table_data_e1 :
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csem_int_table_data_e1h;
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else
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IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
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data = is_e1 ? usem_int_table_data_e1 :
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usem_int_table_data_e1h;
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else
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IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
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data = is_e1 ? xsem_int_table_data_e1 :
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xsem_int_table_data_e1h;
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else
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IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
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data = is_e1 ? tsem_pram_data_e1 : tsem_pram_data_e1h;
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else
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IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
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data = is_e1 ? csem_pram_data_e1 : csem_pram_data_e1h;
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else
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IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
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data = is_e1 ? usem_pram_data_e1 : usem_pram_data_e1h;
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else
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IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
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data = is_e1 ? xsem_pram_data_e1 : xsem_pram_data_e1h;
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return data;
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}
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static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
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u32 len, int gunzip)
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u32 len, int gunzip, int is_e1, u32 blob_off)
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{
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int offset = 0;
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data = bnx2x_sel_blob(addr, data, is_e1) + blob_off;
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if (gunzip) {
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int rc;
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#ifdef __BIG_ENDIAN
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@ -136,64 +273,59 @@ static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
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#endif
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rc = bnx2x_gunzip(bp, (u8 *)data, len);
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if (rc) {
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DP(NETIF_MSG_HW, "gunzip failed ! rc %d\n", rc);
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BNX2X_ERR("gunzip failed ! rc %d\n", rc);
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return;
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}
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len = bp->gunzip_outlen;
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#ifdef __BIG_ENDIAN
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kfree(temp);
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for (i = 0; i < len; i++)
|
||||
((u32 *)bp->gunzip_buf)[i] =
|
||||
((u32 *)bp->gunzip_buf)[i] =
|
||||
swab32(((u32 *)bp->gunzip_buf)[i]);
|
||||
#endif
|
||||
} else {
|
||||
if ((len * 4) > FW_BUF_SIZE) {
|
||||
BNX2X_ERR("LARGE DMAE OPERATION ! len 0x%x\n", len*4);
|
||||
BNX2X_ERR("LARGE DMAE OPERATION ! "
|
||||
"addr 0x%x len 0x%x\n", addr, len*4);
|
||||
return;
|
||||
}
|
||||
memcpy(bp->gunzip_buf, data, len * 4);
|
||||
}
|
||||
|
||||
while (len > DMAE_LEN32_MAX) {
|
||||
if (bp->dmae_ready) {
|
||||
while (len > DMAE_LEN32_WR_MAX) {
|
||||
bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
|
||||
addr + offset, DMAE_LEN32_WR_MAX);
|
||||
offset += DMAE_LEN32_WR_MAX * 4;
|
||||
len -= DMAE_LEN32_WR_MAX;
|
||||
}
|
||||
bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
|
||||
addr + offset, DMAE_LEN32_MAX);
|
||||
offset += DMAE_LEN32_MAX * 4;
|
||||
len -= DMAE_LEN32_MAX;
|
||||
}
|
||||
bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, addr + offset, len);
|
||||
}
|
||||
|
||||
#define INIT_MEM_WB(reg, data, reg_off, len) \
|
||||
bnx2x_init_wr_wb(bp, reg + reg_off*4, data, len, 0)
|
||||
|
||||
#define INIT_GUNZIP_DMAE(reg, data, reg_off, len) \
|
||||
bnx2x_init_wr_wb(bp, reg + reg_off*4, data, len, 1)
|
||||
|
||||
static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
|
||||
{
|
||||
int offset = 0;
|
||||
|
||||
if ((len * 4) > FW_BUF_SIZE) {
|
||||
BNX2X_ERR("LARGE DMAE OPERATION ! len 0x%x\n", len * 4);
|
||||
return;
|
||||
}
|
||||
memset(bp->gunzip_buf, fill, len * 4);
|
||||
|
||||
while (len > DMAE_LEN32_MAX) {
|
||||
bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
|
||||
addr + offset, DMAE_LEN32_MAX);
|
||||
offset += DMAE_LEN32_MAX * 4;
|
||||
len -= DMAE_LEN32_MAX;
|
||||
}
|
||||
bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, addr + offset, len);
|
||||
addr + offset, len);
|
||||
} else
|
||||
bnx2x_init_ind_wr(bp, addr, bp->gunzip_buf, len);
|
||||
}
|
||||
|
||||
static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
|
||||
{
|
||||
int i;
|
||||
int is_e1 = CHIP_IS_E1(bp);
|
||||
int is_e1h = CHIP_IS_E1H(bp);
|
||||
int is_emul_e1h = (CHIP_REV_IS_EMUL(bp) && is_e1h);
|
||||
int hw_wr, i;
|
||||
union init_op *op;
|
||||
u32 op_type, addr, len;
|
||||
const u32 *data;
|
||||
const u32 *data, *data_base;
|
||||
|
||||
if (CHIP_REV_IS_FPGA(bp))
|
||||
hw_wr = OP_WR_FPGA;
|
||||
else if (CHIP_REV_IS_EMUL(bp))
|
||||
hw_wr = OP_WR_EMUL;
|
||||
else
|
||||
hw_wr = OP_WR_ASIC;
|
||||
|
||||
if (is_e1)
|
||||
data_base = init_data_e1;
|
||||
else /* CHIP_IS_E1H(bp) */
|
||||
data_base = init_data_e1h;
|
||||
|
||||
for (i = op_start; i < op_end; i++) {
|
||||
|
||||
|
|
@ -202,7 +334,30 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
|
|||
op_type = op->str_wr.op;
|
||||
addr = op->str_wr.offset;
|
||||
len = op->str_wr.data_len;
|
||||
data = init_data + op->str_wr.data_off;
|
||||
data = data_base + op->str_wr.data_off;
|
||||
|
||||
/* carefull! it must be in order */
|
||||
if (unlikely(op_type > OP_WB)) {
|
||||
|
||||
/* If E1 only */
|
||||
if (op_type <= OP_WB_E1) {
|
||||
if (is_e1)
|
||||
op_type -= (OP_RD_E1 - OP_RD);
|
||||
|
||||
/* If E1H only */
|
||||
} else if (op_type <= OP_WB_E1H) {
|
||||
if (is_e1h)
|
||||
op_type -= (OP_RD_E1H - OP_RD);
|
||||
}
|
||||
|
||||
/* HW/EMUL specific */
|
||||
if (op_type == hw_wr)
|
||||
op_type = OP_WR;
|
||||
|
||||
/* EMUL on E1H is special */
|
||||
if ((op_type == OP_WR_EMUL_E1H) && is_emul_e1h)
|
||||
op_type = OP_WR;
|
||||
}
|
||||
|
||||
switch (op_type) {
|
||||
case OP_RD:
|
||||
|
|
@ -215,7 +370,7 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
|
|||
bnx2x_init_str_wr(bp, addr, data, len);
|
||||
break;
|
||||
case OP_WB:
|
||||
bnx2x_init_wr_wb(bp, addr, data, len, 0);
|
||||
bnx2x_init_wr_wb(bp, addr, data, len, 0, is_e1, 0);
|
||||
break;
|
||||
case OP_SI:
|
||||
bnx2x_init_ind_wr(bp, addr, data, len);
|
||||
|
|
@ -224,10 +379,21 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
|
|||
bnx2x_init_fill(bp, addr, 0, op->zero.len);
|
||||
break;
|
||||
case OP_ZP:
|
||||
bnx2x_init_wr_wb(bp, addr, data, len, 1);
|
||||
bnx2x_init_wr_wb(bp, addr, data, len, 1, is_e1,
|
||||
op->str_wr.data_off);
|
||||
break;
|
||||
case OP_WR_64:
|
||||
bnx2x_init_wr_64(bp, addr, data, len);
|
||||
break;
|
||||
default:
|
||||
BNX2X_ERR("BAD init operation!\n");
|
||||
/* happens whenever an op is of a diff HW */
|
||||
#if 0
|
||||
DP(NETIF_MSG_HW, "skipping init operation "
|
||||
"index %d[%d:%d]: type %d addr 0x%x "
|
||||
"len %d(0x%x)\n",
|
||||
i, op_start, op_end, op_type, addr, len, len);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -238,7 +404,7 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
|
|||
****************************************************************************/
|
||||
/*
|
||||
* This code configures the PCI read/write arbiter
|
||||
* which implements a wighted round robin
|
||||
* which implements a weighted round robin
|
||||
* between the virtual queues in the chip.
|
||||
*
|
||||
* The values were derived for each PCI max payload and max request size.
|
||||
|
|
@ -308,7 +474,7 @@ static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
|
|||
{{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81} }
|
||||
};
|
||||
|
||||
/* register adresses for read queues */
|
||||
/* register addresses for read queues */
|
||||
static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
|
||||
{PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND0},
|
||||
|
|
@ -368,7 +534,7 @@ static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
|
|||
PXP2_REG_PSWRQ_BW_UB28}
|
||||
};
|
||||
|
||||
/* register adresses for wrtie queues */
|
||||
/* register addresses for write queues */
|
||||
static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
|
||||
{PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
|
||||
PXP2_REG_PSWRQ_BW_UB1},
|
||||
|
|
@ -417,6 +583,10 @@ static void bnx2x_init_pxp(struct bnx2x *bp)
|
|||
w_order, MAX_WR_ORD);
|
||||
w_order = MAX_WR_ORD;
|
||||
}
|
||||
if (CHIP_REV_IS_FPGA(bp)) {
|
||||
DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n");
|
||||
w_order = 0;
|
||||
}
|
||||
DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order);
|
||||
|
||||
for (i = 0; i < NUM_RD_Q-1; i++) {
|
||||
|
|
@ -474,7 +644,20 @@ static void bnx2x_init_pxp(struct bnx2x *bp)
|
|||
REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
|
||||
|
||||
REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
|
||||
REG_WR(bp, PXP2_REG_WR_DMAE_TH, (128 << w_order)/16);
|
||||
|
||||
if (CHIP_IS_E1H(bp)) {
|
||||
REG_WR(bp, PXP2_REG_WR_HC_MPS, w_order+1);
|
||||
REG_WR(bp, PXP2_REG_WR_USDM_MPS, w_order+1);
|
||||
REG_WR(bp, PXP2_REG_WR_CSDM_MPS, w_order+1);
|
||||
REG_WR(bp, PXP2_REG_WR_TSDM_MPS, w_order+1);
|
||||
REG_WR(bp, PXP2_REG_WR_XSDM_MPS, w_order+1);
|
||||
REG_WR(bp, PXP2_REG_WR_QM_MPS, w_order+1);
|
||||
REG_WR(bp, PXP2_REG_WR_TM_MPS, w_order+1);
|
||||
REG_WR(bp, PXP2_REG_WR_SRC_MPS, w_order+1);
|
||||
REG_WR(bp, PXP2_REG_WR_DBG_MPS, w_order+1);
|
||||
REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */
|
||||
REG_WR(bp, PXP2_REG_WR_CDU_MPS, w_order+1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -557,6 +740,72 @@ static u8 calc_crc8(u32 data, u8 crc)
|
|||
return crc_res;
|
||||
}
|
||||
|
||||
/* regiesers addresses are not in order
|
||||
so these arrays help simplify the code */
|
||||
static const int cm_start[E1H_FUNC_MAX][9] = {
|
||||
{MISC_FUNC0_START, TCM_FUNC0_START, UCM_FUNC0_START, CCM_FUNC0_START,
|
||||
XCM_FUNC0_START, TSEM_FUNC0_START, USEM_FUNC0_START, CSEM_FUNC0_START,
|
||||
XSEM_FUNC0_START},
|
||||
{MISC_FUNC1_START, TCM_FUNC1_START, UCM_FUNC1_START, CCM_FUNC1_START,
|
||||
XCM_FUNC1_START, TSEM_FUNC1_START, USEM_FUNC1_START, CSEM_FUNC1_START,
|
||||
XSEM_FUNC1_START},
|
||||
{MISC_FUNC2_START, TCM_FUNC2_START, UCM_FUNC2_START, CCM_FUNC2_START,
|
||||
XCM_FUNC2_START, TSEM_FUNC2_START, USEM_FUNC2_START, CSEM_FUNC2_START,
|
||||
XSEM_FUNC2_START},
|
||||
{MISC_FUNC3_START, TCM_FUNC3_START, UCM_FUNC3_START, CCM_FUNC3_START,
|
||||
XCM_FUNC3_START, TSEM_FUNC3_START, USEM_FUNC3_START, CSEM_FUNC3_START,
|
||||
XSEM_FUNC3_START},
|
||||
{MISC_FUNC4_START, TCM_FUNC4_START, UCM_FUNC4_START, CCM_FUNC4_START,
|
||||
XCM_FUNC4_START, TSEM_FUNC4_START, USEM_FUNC4_START, CSEM_FUNC4_START,
|
||||
XSEM_FUNC4_START},
|
||||
{MISC_FUNC5_START, TCM_FUNC5_START, UCM_FUNC5_START, CCM_FUNC5_START,
|
||||
XCM_FUNC5_START, TSEM_FUNC5_START, USEM_FUNC5_START, CSEM_FUNC5_START,
|
||||
XSEM_FUNC5_START},
|
||||
{MISC_FUNC6_START, TCM_FUNC6_START, UCM_FUNC6_START, CCM_FUNC6_START,
|
||||
XCM_FUNC6_START, TSEM_FUNC6_START, USEM_FUNC6_START, CSEM_FUNC6_START,
|
||||
XSEM_FUNC6_START},
|
||||
{MISC_FUNC7_START, TCM_FUNC7_START, UCM_FUNC7_START, CCM_FUNC7_START,
|
||||
XCM_FUNC7_START, TSEM_FUNC7_START, USEM_FUNC7_START, CSEM_FUNC7_START,
|
||||
XSEM_FUNC7_START}
|
||||
};
|
||||
|
||||
static const int cm_end[E1H_FUNC_MAX][9] = {
|
||||
{MISC_FUNC0_END, TCM_FUNC0_END, UCM_FUNC0_END, CCM_FUNC0_END,
|
||||
XCM_FUNC0_END, TSEM_FUNC0_END, USEM_FUNC0_END, CSEM_FUNC0_END,
|
||||
XSEM_FUNC0_END},
|
||||
{MISC_FUNC1_END, TCM_FUNC1_END, UCM_FUNC1_END, CCM_FUNC1_END,
|
||||
XCM_FUNC1_END, TSEM_FUNC1_END, USEM_FUNC1_END, CSEM_FUNC1_END,
|
||||
XSEM_FUNC1_END},
|
||||
{MISC_FUNC2_END, TCM_FUNC2_END, UCM_FUNC2_END, CCM_FUNC2_END,
|
||||
XCM_FUNC2_END, TSEM_FUNC2_END, USEM_FUNC2_END, CSEM_FUNC2_END,
|
||||
XSEM_FUNC2_END},
|
||||
{MISC_FUNC3_END, TCM_FUNC3_END, UCM_FUNC3_END, CCM_FUNC3_END,
|
||||
XCM_FUNC3_END, TSEM_FUNC3_END, USEM_FUNC3_END, CSEM_FUNC3_END,
|
||||
XSEM_FUNC3_END},
|
||||
{MISC_FUNC4_END, TCM_FUNC4_END, UCM_FUNC4_END, CCM_FUNC4_END,
|
||||
XCM_FUNC4_END, TSEM_FUNC4_END, USEM_FUNC4_END, CSEM_FUNC4_END,
|
||||
XSEM_FUNC4_END},
|
||||
{MISC_FUNC5_END, TCM_FUNC5_END, UCM_FUNC5_END, CCM_FUNC5_END,
|
||||
XCM_FUNC5_END, TSEM_FUNC5_END, USEM_FUNC5_END, CSEM_FUNC5_END,
|
||||
XSEM_FUNC5_END},
|
||||
{MISC_FUNC6_END, TCM_FUNC6_END, UCM_FUNC6_END, CCM_FUNC6_END,
|
||||
XCM_FUNC6_END, TSEM_FUNC6_END, USEM_FUNC6_END, CSEM_FUNC6_END,
|
||||
XSEM_FUNC6_END},
|
||||
{MISC_FUNC7_END, TCM_FUNC7_END, UCM_FUNC7_END, CCM_FUNC7_END,
|
||||
XCM_FUNC7_END, TSEM_FUNC7_END, USEM_FUNC7_END, CSEM_FUNC7_END,
|
||||
XSEM_FUNC7_END},
|
||||
};
|
||||
|
||||
static const int hc_limits[E1H_FUNC_MAX][2] = {
|
||||
{HC_FUNC0_START, HC_FUNC0_END},
|
||||
{HC_FUNC1_START, HC_FUNC1_END},
|
||||
{HC_FUNC2_START, HC_FUNC2_END},
|
||||
{HC_FUNC3_START, HC_FUNC3_END},
|
||||
{HC_FUNC4_START, HC_FUNC4_END},
|
||||
{HC_FUNC5_START, HC_FUNC5_END},
|
||||
{HC_FUNC6_START, HC_FUNC6_END},
|
||||
{HC_FUNC7_START, HC_FUNC7_END}
|
||||
};
|
||||
|
||||
#endif /* BNX2X_INIT_H */
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -137,7 +137,6 @@ static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
|
|||
PCICFG_VENDOR_ID_OFFSET);
|
||||
}
|
||||
|
||||
#ifdef BNX2X_IND_RD
|
||||
static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
|
||||
{
|
||||
u32 val;
|
||||
|
|
@ -149,7 +148,6 @@ static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
|
|||
|
||||
return val;
|
||||
}
|
||||
#endif
|
||||
|
||||
static const u32 dmae_reg_go_c[] = {
|
||||
DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
|
||||
|
|
@ -169,19 +167,29 @@ static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
|
|||
for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
|
||||
REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
|
||||
|
||||
/* DP(NETIF_MSG_DMAE, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
|
||||
idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); */
|
||||
DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
|
||||
idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
|
||||
}
|
||||
REG_WR(bp, dmae_reg_go_c[idx], 1);
|
||||
}
|
||||
|
||||
void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
|
||||
u32 dst_addr, u32 len32)
|
||||
void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
|
||||
u32 len32)
|
||||
{
|
||||
struct dmae_command *dmae = &bp->dmae;
|
||||
int port = bp->port;
|
||||
struct dmae_command *dmae = &bp->init_dmae;
|
||||
u32 *wb_comp = bnx2x_sp(bp, wb_comp);
|
||||
int timeout = 200;
|
||||
int cnt = 200;
|
||||
|
||||
if (!bp->dmae_ready) {
|
||||
u32 *data = bnx2x_sp(bp, wb_data[0]);
|
||||
|
||||
DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
|
||||
" using indirect\n", dst_addr, len32);
|
||||
bnx2x_init_ind_wr(bp, dst_addr, data, len32);
|
||||
return;
|
||||
}
|
||||
|
||||
mutex_lock(&bp->dmae_mutex);
|
||||
|
||||
memset(dmae, 0, sizeof(struct dmae_command));
|
||||
|
||||
|
|
@ -193,7 +201,7 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
|
|||
#else
|
||||
DMAE_CMD_ENDIANITY_DW_SWAP |
|
||||
#endif
|
||||
(port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
|
||||
(bp->port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
|
||||
dmae->src_addr_lo = U64_LO(dma_addr);
|
||||
dmae->src_addr_hi = U64_HI(dma_addr);
|
||||
dmae->dst_addr_lo = dst_addr >> 2;
|
||||
|
|
@ -201,48 +209,62 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
|
|||
dmae->len = len32;
|
||||
dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
|
||||
dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
|
||||
dmae->comp_val = BNX2X_WB_COMP_VAL;
|
||||
dmae->comp_val = DMAE_COMP_VAL;
|
||||
|
||||
/*
|
||||
DP(NETIF_MSG_DMAE, "dmae: opcode 0x%08x\n"
|
||||
DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
|
||||
DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
|
||||
"dst_addr [%x:%08x (%08x)]\n"
|
||||
DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
|
||||
dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
|
||||
dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr,
|
||||
dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
|
||||
*/
|
||||
/*
|
||||
DP(NETIF_MSG_DMAE, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
|
||||
DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
|
||||
bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
|
||||
bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
|
||||
*/
|
||||
|
||||
*wb_comp = 0;
|
||||
|
||||
bnx2x_post_dmae(bp, dmae, port * 8);
|
||||
bnx2x_post_dmae(bp, dmae, (bp->port)*MAX_DMAE_C_PER_PORT);
|
||||
|
||||
udelay(5);
|
||||
/* adjust timeout for emulation/FPGA */
|
||||
if (CHIP_REV_IS_SLOW(bp))
|
||||
timeout *= 100;
|
||||
while (*wb_comp != BNX2X_WB_COMP_VAL) {
|
||||
/* DP(NETIF_MSG_DMAE, "wb_comp 0x%08x\n", *wb_comp); */
|
||||
udelay(5);
|
||||
if (!timeout) {
|
||||
|
||||
while (*wb_comp != DMAE_COMP_VAL) {
|
||||
DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
|
||||
|
||||
/* adjust delay for emulation/FPGA */
|
||||
if (CHIP_REV_IS_SLOW(bp))
|
||||
msleep(100);
|
||||
else
|
||||
udelay(5);
|
||||
|
||||
if (!cnt) {
|
||||
BNX2X_ERR("dmae timeout!\n");
|
||||
break;
|
||||
}
|
||||
timeout--;
|
||||
cnt--;
|
||||
}
|
||||
|
||||
mutex_unlock(&bp->dmae_mutex);
|
||||
}
|
||||
|
||||
void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
|
||||
{
|
||||
struct dmae_command *dmae = &bp->dmae;
|
||||
int port = bp->port;
|
||||
struct dmae_command *dmae = &bp->init_dmae;
|
||||
u32 *wb_comp = bnx2x_sp(bp, wb_comp);
|
||||
int timeout = 200;
|
||||
int cnt = 200;
|
||||
|
||||
if (!bp->dmae_ready) {
|
||||
u32 *data = bnx2x_sp(bp, wb_data[0]);
|
||||
int i;
|
||||
|
||||
DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
|
||||
" using indirect\n", src_addr, len32);
|
||||
for (i = 0; i < len32; i++)
|
||||
data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
|
||||
return;
|
||||
}
|
||||
|
||||
mutex_lock(&bp->dmae_mutex);
|
||||
|
||||
memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
|
||||
memset(dmae, 0, sizeof(struct dmae_command));
|
||||
|
|
@ -255,7 +277,7 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
|
|||
#else
|
||||
DMAE_CMD_ENDIANITY_DW_SWAP |
|
||||
#endif
|
||||
(port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
|
||||
(bp->port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
|
||||
dmae->src_addr_lo = src_addr >> 2;
|
||||
dmae->src_addr_hi = 0;
|
||||
dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
|
||||
|
|
@ -263,38 +285,64 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
|
|||
dmae->len = len32;
|
||||
dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
|
||||
dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
|
||||
dmae->comp_val = BNX2X_WB_COMP_VAL;
|
||||
dmae->comp_val = DMAE_COMP_VAL;
|
||||
|
||||
/*
|
||||
DP(NETIF_MSG_DMAE, "dmae: opcode 0x%08x\n"
|
||||
DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
|
||||
DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
|
||||
"dst_addr [%x:%08x (%08x)]\n"
|
||||
DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
|
||||
dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
|
||||
dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr,
|
||||
dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
|
||||
*/
|
||||
|
||||
*wb_comp = 0;
|
||||
|
||||
bnx2x_post_dmae(bp, dmae, port * 8);
|
||||
bnx2x_post_dmae(bp, dmae, (bp->port)*MAX_DMAE_C_PER_PORT);
|
||||
|
||||
udelay(5);
|
||||
while (*wb_comp != BNX2X_WB_COMP_VAL) {
|
||||
udelay(5);
|
||||
if (!timeout) {
|
||||
|
||||
while (*wb_comp != DMAE_COMP_VAL) {
|
||||
|
||||
/* adjust delay for emulation/FPGA */
|
||||
if (CHIP_REV_IS_SLOW(bp))
|
||||
msleep(100);
|
||||
else
|
||||
udelay(5);
|
||||
|
||||
if (!cnt) {
|
||||
BNX2X_ERR("dmae timeout!\n");
|
||||
break;
|
||||
}
|
||||
timeout--;
|
||||
cnt--;
|
||||
}
|
||||
/*
|
||||
DP(NETIF_MSG_DMAE, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
|
||||
DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
|
||||
bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
|
||||
bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
|
||||
*/
|
||||
|
||||
mutex_unlock(&bp->dmae_mutex);
|
||||
}
|
||||
|
||||
/* used only for slowpath so not inlined */
|
||||
static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
|
||||
{
|
||||
u32 wb_write[2];
|
||||
|
||||
wb_write[0] = val_hi;
|
||||
wb_write[1] = val_lo;
|
||||
REG_WR_DMAE(bp, reg, wb_write, 2);
|
||||
}
|
||||
|
||||
#ifdef USE_WB_RD
|
||||
static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
|
||||
{
|
||||
u32 wb_data[2];
|
||||
|
||||
REG_RD_DMAE(bp, reg, wb_data, 2);
|
||||
|
||||
return HILO_U64(wb_data[0], wb_data[1]);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int bnx2x_mc_assert(struct bnx2x *bp)
|
||||
{
|
||||
int i, j, rc = 0;
|
||||
|
|
@ -3438,17 +3486,12 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
|
|||
int count, i;
|
||||
u32 val = 0;
|
||||
|
||||
switch (CHIP_REV(bp)) {
|
||||
case CHIP_REV_EMUL:
|
||||
factor = 200;
|
||||
break;
|
||||
case CHIP_REV_FPGA:
|
||||
if (CHIP_REV_IS_FPGA(bp))
|
||||
factor = 120;
|
||||
break;
|
||||
default:
|
||||
else if (CHIP_REV_IS_EMUL(bp))
|
||||
factor = 200;
|
||||
else
|
||||
factor = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
DP(NETIF_MSG_HW, "start part1\n");
|
||||
|
||||
|
|
@ -3777,10 +3820,14 @@ static int bnx2x_function_init(struct bnx2x *bp, int mode)
|
|||
bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END);
|
||||
bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END);
|
||||
|
||||
bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE);
|
||||
bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE);
|
||||
bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE);
|
||||
bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE);
|
||||
bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
|
||||
STORM_INTMEM_SIZE_E1);
|
||||
bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
|
||||
STORM_INTMEM_SIZE_E1);
|
||||
bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
|
||||
STORM_INTMEM_SIZE_E1);
|
||||
bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
|
||||
STORM_INTMEM_SIZE_E1);
|
||||
|
||||
bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END);
|
||||
bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END);
|
||||
|
|
@ -3990,8 +4037,7 @@ static int bnx2x_function_init(struct bnx2x *bp, int mode)
|
|||
#endif
|
||||
/* Port DQ comes here */
|
||||
/* Port BRB1 comes here */
|
||||
bnx2x_init_block(bp, func ? PRS_PORT1_START : PRS_PORT0_START,
|
||||
func ? PRS_PORT1_END : PRS_PORT0_END);
|
||||
/* Port PRS comes here */
|
||||
/* Port TSDM comes here */
|
||||
/* Port CSDM comes here */
|
||||
/* Port USDM comes here */
|
||||
|
|
@ -7264,12 +7310,6 @@ static int __devinit bnx2x_init_board(struct pci_dev *pdev,
|
|||
|
||||
bnx2x_get_hwinfo(bp);
|
||||
|
||||
if (CHIP_REV(bp) == CHIP_REV_FPGA) {
|
||||
printk(KERN_ERR PFX "FPGA detected. MCP disabled,"
|
||||
" will only init first device\n");
|
||||
onefunc = 1;
|
||||
nomcp = 1;
|
||||
}
|
||||
|
||||
if (nomcp) {
|
||||
printk(KERN_ERR PFX "MCP disabled, will only"
|
||||
|
|
|
|||
Loading…
Reference in New Issue