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drm/amd/pp: Remove cgs_query_system_info 

Get gpu info through adev directly in powerplay

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hifive-unleashed-5.1
Rex Zhu 2018-02-27 19:15:08 +08:00 committed by Alex Deucher
parent 6848d73e88
commit ada6770e95
14 changed files with 72 additions and 286 deletions
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59
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
View File

@ -835,64 +835,6 @@ static int amdgpu_cgs_is_virtualization_enabled(void *cgs_device)
return amdgpu_sriov_vf(adev);
}
static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device,
struct cgs_system_info *sys_info)
{
CGS_FUNC_ADEV;
if (NULL == sys_info)
return -ENODEV;
if (sizeof(struct cgs_system_info) != sys_info->size)
return -ENODEV;
switch (sys_info->info_id) {
case CGS_SYSTEM_INFO_ADAPTER_BDF_ID:
sys_info->value = adev->pdev->devfn | (adev->pdev->bus->number << 8);
break;
case CGS_SYSTEM_INFO_PCIE_GEN_INFO:
sys_info->value = adev->pm.pcie_gen_mask;
break;
case CGS_SYSTEM_INFO_PCIE_MLW:
sys_info->value = adev->pm.pcie_mlw_mask;
break;
case CGS_SYSTEM_INFO_PCIE_DEV:
sys_info->value = adev->pdev->device;
break;
case CGS_SYSTEM_INFO_PCIE_REV:
sys_info->value = adev->pdev->revision;
break;
case CGS_SYSTEM_INFO_CG_FLAGS:
sys_info->value = adev->cg_flags;
break;
case CGS_SYSTEM_INFO_PG_FLAGS:
sys_info->value = adev->pg_flags;
break;
case CGS_SYSTEM_INFO_GFX_CU_INFO:
sys_info->value = adev->gfx.cu_info.number;
break;
case CGS_SYSTEM_INFO_GFX_SE_INFO:
sys_info->value = adev->gfx.config.max_shader_engines;
break;
case CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID:
sys_info->value = adev->pdev->subsystem_device;
break;
case CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID:
sys_info->value = adev->pdev->subsystem_vendor;
break;
case CGS_SYSTEM_INFO_PCIE_BUS_DEVFN:
sys_info->value = adev->pdev->devfn;
break;
case CGS_SYSTEM_INFO_VRAM_WIDTH:
sys_info->value = adev->gmc.vram_width;
break;
default:
return -ENODEV;
}
return 0;
}
static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
struct cgs_display_info *info)
{
@ -996,7 +938,6 @@ static const struct cgs_ops amdgpu_cgs_ops = {
.set_clockgating_state = amdgpu_cgs_set_clockgating_state,
.get_active_displays_info = amdgpu_cgs_get_active_displays_info,
.notify_dpm_enabled = amdgpu_cgs_notify_dpm_enabled,
.query_system_info = amdgpu_cgs_query_system_info,
.is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,
.enter_safe_mode = amdgpu_cgs_enter_safe_mode,
.lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,

34
drivers/gpu/drm/amd/include/cgs_common.h
View File

@ -88,33 +88,6 @@ enum cgs_ucode_id {
CGS_UCODE_ID_MAXIMUM,
};
enum cgs_system_info_id {
CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1,
CGS_SYSTEM_INFO_PCIE_GEN_INFO,
CGS_SYSTEM_INFO_PCIE_MLW,
CGS_SYSTEM_INFO_PCIE_DEV,
CGS_SYSTEM_INFO_PCIE_REV,
CGS_SYSTEM_INFO_CG_FLAGS,
CGS_SYSTEM_INFO_PG_FLAGS,
CGS_SYSTEM_INFO_GFX_CU_INFO,
CGS_SYSTEM_INFO_GFX_SE_INFO,
CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID,
CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID,
CGS_SYSTEM_INFO_PCIE_BUS_DEVFN,
CGS_SYSTEM_INFO_VRAM_WIDTH,
CGS_SYSTEM_INFO_ID_MAXIMUM,
};
struct cgs_system_info {
uint64_t size;
enum cgs_system_info_id info_id;
union {
void *ptr;
uint64_t value;
};
uint64_t padding[13];
};
/*
* enum cgs_resource_type - GPU resource type
*/
@ -375,9 +348,6 @@ typedef int(*cgs_get_active_displays_info)(
typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled);
typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device,
struct cgs_system_info *sys_info);
typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device);
typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en);
@ -416,8 +386,6 @@ struct cgs_ops {
cgs_get_active_displays_info get_active_displays_info;
/* notify dpm enabled */
cgs_notify_dpm_enabled notify_dpm_enabled;
/* get system info */
cgs_query_system_info query_system_info;
cgs_is_virtualization_enabled_t is_virtualization_enabled;
cgs_enter_safe_mode enter_safe_mode;
cgs_lock_grbm_idx lock_grbm_idx;
@ -483,8 +451,6 @@ struct cgs_device
#define cgs_get_active_displays_info(dev, info) \
CGS_CALL(get_active_displays_info, dev, info)
#define cgs_query_system_info(dev, sys_info) \
CGS_CALL(query_system_info, dev, sys_info)
#define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \
resource_base) \
CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \

22
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
View File

@ -173,8 +173,7 @@ static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
struct cgs_system_info sys_info = {0};
int result;
struct amdgpu_device *adev = hwmgr->adev;
cz_hwmgr->gfx_ramp_step = 256*25/100;
cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
@ -234,17 +233,14 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_UVDPowerGating);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_VCEPowerGating);
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
result = cgs_query_system_info(hwmgr->device, &sys_info);
if (!result) {
if (sys_info.value & AMD_PG_SUPPORT_UVD)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDPowerGating);
if (sys_info.value & AMD_PG_SUPPORT_VCE)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_VCEPowerGating);
}
if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDPowerGating);
if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_VCEPowerGating);
return 0;
}

54
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
View File

@ -64,30 +64,16 @@ uint16_t convert_to_vddc(uint8_t vid)
return (uint16_t) ((6200 - (vid * 25)) / VOLTAGE_SCALE);
}
static int phm_get_pci_bus_devfn(struct pp_hwmgr *hwmgr,
struct cgs_system_info *sys_info)
{
sys_info->size = sizeof(struct cgs_system_info);
sys_info->info_id = CGS_SYSTEM_INFO_PCIE_BUS_DEVFN;
return cgs_query_system_info(hwmgr->device, sys_info);
}
static int phm_thermal_l2h_irq(void *private_data,
unsigned src_id, const uint32_t *iv_entry)
{
struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
struct cgs_system_info sys_info = {0};
int result;
struct amdgpu_device *adev = hwmgr->adev;
result = phm_get_pci_bus_devfn(hwmgr, &sys_info);
if (result)
return -EINVAL;
pr_warn("GPU over temperature range detected on PCIe %lld:%lld.%lld!\n",
PCI_BUS_NUM(sys_info.value),
PCI_SLOT(sys_info.value),
PCI_FUNC(sys_info.value));
pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
PCI_BUS_NUM(adev->pdev->devfn),
PCI_SLOT(adev->pdev->devfn),
PCI_FUNC(adev->pdev->devfn));
return 0;
}
@ -95,17 +81,12 @@ static int phm_thermal_h2l_irq(void *private_data,
unsigned src_id, const uint32_t *iv_entry)
{
struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
struct cgs_system_info sys_info = {0};
int result;
struct amdgpu_device *adev = hwmgr->adev;
result = phm_get_pci_bus_devfn(hwmgr, &sys_info);
if (result)
return -EINVAL;
pr_warn("GPU under temperature range detected on PCIe %lld:%lld.%lld!\n",
PCI_BUS_NUM(sys_info.value),
PCI_SLOT(sys_info.value),
PCI_FUNC(sys_info.value));
pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
PCI_BUS_NUM(adev->pdev->devfn),
PCI_SLOT(adev->pdev->devfn),
PCI_FUNC(adev->pdev->devfn));
return 0;
}
@ -113,17 +94,12 @@ static int phm_ctf_irq(void *private_data,
unsigned src_id, const uint32_t *iv_entry)
{
struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
struct cgs_system_info sys_info = {0};
int result;
struct amdgpu_device *adev = hwmgr->adev;
result = phm_get_pci_bus_devfn(hwmgr, &sys_info);
if (result)
return -EINVAL;
pr_warn("GPU Critical Temperature Fault detected on PCIe %lld:%lld.%lld!\n",
PCI_BUS_NUM(sys_info.value),
PCI_SLOT(sys_info.value),
PCI_FUNC(sys_info.value));
pr_warn("GPU Critical Temperature Fault detected on PCIe %d:%d.%d!\n",
PCI_BUS_NUM(adev->pdev->devfn),
PCI_SLOT(adev->pdev->devfn),
PCI_FUNC(adev->pdev->devfn));
return 0;
}

17
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
View File

@ -472,23 +472,12 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
*/
int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)
{
struct cgs_system_info sys_info = {0};
uint32_t active_cus;
int result;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO;
result = cgs_query_system_info(hwmgr->device, &sys_info);
if (result)
return -EINVAL;
active_cus = sys_info.value;
struct amdgpu_device *adev = hwmgr->adev;
if (enable)
return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus);
PPSMC_MSG_GFX_CU_PG_ENABLE,
adev->gfx.cu_info.number);
else
return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GFX_CU_PG_DISABLE);

57
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
View File

@ -1468,8 +1468,7 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
struct cgs_system_info sys_info = {0};
int result;
struct amdgpu_device *adev = hwmgr->adev;
data->dll_default_on = false;
data->mclk_dpm0_activity_target = 0xa;
@ -1590,17 +1589,13 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
data->pcie_lane_power_saving.max = 0;
data->pcie_lane_power_saving.min = 16;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
result = cgs_query_system_info(hwmgr->device, &sys_info);
if (!result) {
if (sys_info.value & AMD_PG_SUPPORT_UVD)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDPowerGating);
if (sys_info.value & AMD_PG_SUPPORT_VCE)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_VCEPowerGating);
}
if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDPowerGating);
if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_VCEPowerGating);
}
/**
@ -2035,7 +2030,7 @@ static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
struct phm_ppt_v1_voltage_lookup_table *lookup_table;
uint32_t i;
uint32_t hw_revision, sub_vendor_id, sub_sys_id;
struct cgs_system_info sys_info = {0};
struct amdgpu_device *adev = hwmgr->adev;
if (table_info != NULL) {
dep_mclk_table = table_info->vdd_dep_on_mclk;
@ -2043,19 +2038,9 @@ static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
} else
return 0;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
cgs_query_system_info(hwmgr->device, &sys_info);
hw_revision = (uint32_t)sys_info.value;
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID;
cgs_query_system_info(hwmgr->device, &sys_info);
sub_sys_id = (uint32_t)sys_info.value;
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID;
cgs_query_system_info(hwmgr->device, &sys_info);
sub_vendor_id = (uint32_t)sys_info.value;
hw_revision = adev->pdev->revision;
sub_sys_id = adev->pdev->subsystem_device;
sub_vendor_id = adev->pdev->subsystem_vendor;
if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 &&
((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
@ -2498,7 +2483,7 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
if (0 == result) {
struct cgs_system_info sys_info = {0};
struct amdgpu_device *adev = hwmgr->adev;
data->is_tlu_enabled = false;
@ -2507,22 +2492,10 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
result = cgs_query_system_info(hwmgr->device, &sys_info);
if (result)
data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
else
data->pcie_gen_cap = (uint32_t)sys_info.value;
data->pcie_gen_cap = adev->pm.pcie_gen_mask;
if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
data->pcie_spc_cap = 20;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
result = cgs_query_system_info(hwmgr->device, &sys_info);
if (result)
data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK;
else
data->pcie_lane_cap = (uint32_t)sys_info.value;
data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */

9
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
View File

@ -731,14 +731,9 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
int result;
uint32_t num_se = 0;
uint32_t count, value, value2;
struct cgs_system_info sys_info = {0};
struct amdgpu_device *adev = hwmgr->adev;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
result = cgs_query_system_info(hwmgr->device, &sys_info);
if (result == 0)
num_se = sys_info.value;
num_se = adev->gfx.config.max_shader_engines;
if (PP_CAP(PHM_PlatformCaps_SQRamping) ||
PP_CAP(PHM_PlatformCaps_DBRamping) ||

18
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
View File

@ -190,8 +190,7 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
(struct vega10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)hwmgr->pptable;
struct cgs_system_info sys_info = {0};
int result;
struct amdgpu_device *adev = hwmgr->adev;
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep);
@ -206,15 +205,11 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_EnableSMU7ThermalManagement);
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
result = cgs_query_system_info(hwmgr->device, &sys_info);
if (!result && (sys_info.value & AMD_PG_SUPPORT_UVD))
if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDPowerGating);
if (!result && (sys_info.value & AMD_PG_SUPPORT_VCE))
if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_VCEPowerGating);
@ -750,7 +745,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
struct vega10_hwmgr *data;
uint32_t config_telemetry = 0;
struct pp_atomfwctrl_voltage_table vol_table;
struct cgs_system_info sys_info = {0};
struct amdgpu_device *adev = hwmgr->adev;
uint32_t reg;
data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
@ -843,10 +838,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr->platform_descriptor.clockStep.engineClock = 500;
hwmgr->platform_descriptor.clockStep.memoryClock = 500;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO;
result = cgs_query_system_info(hwmgr->device, &sys_info);
data->total_active_cus = sys_info.value;
data->total_active_cus = adev->gfx.cu_info.number;
/* Setup default Overdrive Fan control settings */
data->odn_fan_table.target_fan_speed =
hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;

28
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
View File

@ -933,13 +933,10 @@ static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
{
int result;
uint32_t num_se = 0, count, data;
struct cgs_system_info sys_info = {0};
struct amdgpu_device *adev = hwmgr->adev;
uint32_t reg;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
if (cgs_query_system_info(hwmgr->device, &sys_info) == 0)
num_se = sys_info.value;
num_se = adev->gfx.config.max_shader_engines;
cgs_enter_safe_mode(hwmgr->device, true);
@ -987,13 +984,10 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
{
int result;
uint32_t num_se = 0, count, data;
struct cgs_system_info sys_info = {0};
struct amdgpu_device *adev = hwmgr->adev;
uint32_t reg;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
if (cgs_query_system_info(hwmgr->device, &sys_info) == 0)
num_se = sys_info.value;
num_se = adev->gfx.config.max_shader_engines;
cgs_enter_safe_mode(hwmgr->device, true);
@ -1052,13 +1046,10 @@ static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr)
{
int result;
uint32_t num_se = 0, count, data;
struct cgs_system_info sys_info = {0};
struct amdgpu_device *adev = hwmgr->adev;
uint32_t reg;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
if (cgs_query_system_info(hwmgr->device, &sys_info) == 0)
num_se = sys_info.value;
num_se = adev->gfx.config.max_shader_engines;
cgs_enter_safe_mode(hwmgr->device, true);
@ -1103,13 +1094,10 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
int result;
uint32_t num_se = 0;
uint32_t count, data;
struct cgs_system_info sys_info = {0};
struct amdgpu_device *adev = hwmgr->adev;
uint32_t reg;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
if (cgs_query_system_info(hwmgr->device, &sys_info) == 0)
num_se = sys_info.value;
num_se = adev->gfx.config.max_shader_engines;
cgs_enter_safe_mode(hwmgr->device, true);

13
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
View File

@ -688,9 +688,9 @@ static int get_dcefclk_voltage_dependency_table(
uint8_t num_entries;
struct phm_ppt_v1_clock_voltage_dependency_table
*clk_table;
struct cgs_system_info sys_info = {0};
uint32_t dev_id;
uint32_t rev_id;
struct amdgpu_device *adev = hwmgr->adev;
PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
"Invalid PowerPlay Table!", return -1);
@ -701,15 +701,8 @@ static int get_dcefclk_voltage_dependency_table(
* This DPM level was added to support 3DPM monitors @ 4K120Hz
*
*/
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
cgs_query_system_info(hwmgr->device, &sys_info);
dev_id = (uint32_t)sys_info.value;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
cgs_query_system_info(hwmgr->device, &sys_info);
rev_id = (uint32_t)sys_info.value;
dev_id = adev->pdev->device;
rev_id = adev->pdev->revision;
if (dev_id == 0x6863 && rev_id == 0 &&
clk_dep_table->entries[clk_dep_table->ucNumEntries - 1].ulClk < 90000)

14
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
View File

@ -236,13 +236,10 @@ static int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
{
struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
struct cgs_system_info sys_info = {0};
struct amdgpu_device *adev = hwmgr->adev;
uint32_t dev_id;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
cgs_query_system_info(hwmgr->device, &sys_info);
dev_id = (uint32_t)sys_info.value;
dev_id = adev->pdev->device;
switch (dev_id) {
case 0x67BA:
@ -1309,7 +1306,7 @@ static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
struct smu7_dpm_table *dpm_table = &data->dpm_table;
int result;
struct cgs_system_info sys_info = {0};
struct amdgpu_device *adev = hwmgr->adev;
uint32_t dev_id;
uint32_t level_array_address = smu_data->dpm_table_start + offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
@ -1330,10 +1327,7 @@ static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
cgs_query_system_info(hwmgr->device, &sys_info);
dev_id = (uint32_t)sys_info.value;
dev_id = adev->pdev->device;
if ((dpm_table->mclk_table.count >= 2)
&& ((dev_id == 0x67B0) || (dev_id == 0x67B1))) {

7
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
View File

@ -281,13 +281,10 @@ static int iceland_smu_init(struct pp_hwmgr *hwmgr)
static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
{
struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
struct cgs_system_info sys_info = {0};
struct amdgpu_device *adev = hwmgr->adev;
uint32_t dev_id;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
cgs_query_system_info(hwmgr->device, &sys_info);
dev_id = (uint32_t)sys_info.value;
dev_id = adev->pdev->device;
switch (dev_id) {
case DEVICE_ID_VI_ICELAND_M_6900:

13
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
View File

@ -1623,19 +1623,12 @@ static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
table_info->vdd_dep_on_sclk;
uint32_t hw_revision, dev_id;
struct cgs_system_info sys_info = {0};
struct amdgpu_device *adev = hwmgr->adev;
stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
cgs_query_system_info(hwmgr->device, &sys_info);
hw_revision = (uint32_t)sys_info.value;
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
cgs_query_system_info(hwmgr->device, &sys_info);
dev_id = (uint32_t)sys_info.value;
hw_revision = adev->pdev->revision;
dev_id = adev->pdev->device;
/* Read SMU_Eefuse to read and calculate RO and determine
* if the part is SS or FF. if RO >= 1660MHz, part is FF.

13
drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
View File

@ -349,7 +349,7 @@ int vega10_set_tools_address(struct pp_hwmgr *hwmgr)
static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr)
{
uint32_t smc_driver_if_version;
struct cgs_system_info sys_info = {0};
struct amdgpu_device *adev = hwmgr->adev;
uint32_t dev_id;
uint32_t rev_id;
@ -359,15 +359,8 @@ static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr)
return -EINVAL);
vega10_read_arg_from_smc(hwmgr, &smc_driver_if_version);
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
cgs_query_system_info(hwmgr->device, &sys_info);
dev_id = (uint32_t)sys_info.value;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
cgs_query_system_info(hwmgr->device, &sys_info);
rev_id = (uint32_t)sys_info.value;
dev_id = adev->pdev->device;
rev_id = adev->pdev->revision;
if (!((dev_id == 0x687f) &&
((rev_id == 0xc0) ||