serial: stm32: adding support for stm32f7
Register offset management rework to support both stm32f4 (default) and stm32f7. Driver rework to ensure same functional level on both stm32f4 and stm32f7: no new feature in this version yet. Signed-off-by: Gerald Baeza <gerald.baeza@st.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>hifive-unleashed-5.1
Alexandre TORGUE
Greg Kroah-Hartman
parent
27b17ae073
commit
ada8618ff3
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@ -1,6 +1,7 @@
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/*
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* Copyright (C) Maxime Coquelin 2015
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* Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
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* Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
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* Gerald Baeza <gerald.baeza@st.com>
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* License terms: GNU General Public License (GPL), version 2
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*
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* Inspired by st-asc.c from STMicroelectronics (c)
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@ -29,16 +30,74 @@
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#define DRIVER_NAME "stm32-usart"
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/* Register offsets */
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#define USART_SR 0x00
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#define USART_DR 0x04
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#define USART_BRR 0x08
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#define USART_CR1 0x0c
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#define USART_CR2 0x10
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#define USART_CR3 0x14
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#define USART_GTPR 0x18
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struct stm32_usart_offsets {
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u8 cr1;
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u8 cr2;
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u8 cr3;
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u8 brr;
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u8 gtpr;
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u8 rtor;
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u8 rqr;
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u8 isr;
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u8 icr;
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u8 rdr;
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u8 tdr;
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};
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/* USART_SR */
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struct stm32_usart_config {
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u8 uart_enable_bit; /* USART_CR1_UE */
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bool has_7bits_data;
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};
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struct stm32_usart_info {
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struct stm32_usart_offsets ofs;
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struct stm32_usart_config cfg;
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};
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#define UNDEF_REG ~0
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/* Register offsets */
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struct stm32_usart_info stm32f4_info = {
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.ofs = {
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.isr = 0x00,
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.rdr = 0x04,
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.tdr = 0x04,
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.brr = 0x08,
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.cr1 = 0x0c,
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.cr2 = 0x10,
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.cr3 = 0x14,
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.gtpr = 0x18,
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.rtor = UNDEF_REG,
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.rqr = UNDEF_REG,
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.icr = UNDEF_REG,
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},
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.cfg = {
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.uart_enable_bit = 13,
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.has_7bits_data = false,
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}
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};
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struct stm32_usart_info stm32f7_info = {
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.ofs = {
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.cr1 = 0x00,
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.cr2 = 0x04,
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.cr3 = 0x08,
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.brr = 0x0c,
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.gtpr = 0x10,
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.rtor = 0x14,
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.rqr = 0x18,
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.isr = 0x1c,
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.icr = 0x20,
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.rdr = 0x24,
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.tdr = 0x28,
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},
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.cfg = {
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.uart_enable_bit = 0,
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.has_7bits_data = true,
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}
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};
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/* USART_SR (F4) / USART_ISR (F7) */
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#define USART_SR_PE BIT(0)
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#define USART_SR_FE BIT(1)
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#define USART_SR_NF BIT(2)
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@ -48,7 +107,16 @@
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#define USART_SR_TC BIT(6)
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#define USART_SR_TXE BIT(7)
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#define USART_SR_LBD BIT(8)
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#define USART_SR_CTS BIT(9)
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#define USART_SR_CTSIF BIT(9)
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#define USART_SR_CTS BIT(10) /* F7 */
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#define USART_SR_RTOF BIT(11) /* F7 */
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#define USART_SR_EOBF BIT(12) /* F7 */
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#define USART_SR_ABRE BIT(14) /* F7 */
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#define USART_SR_ABRF BIT(15) /* F7 */
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#define USART_SR_BUSY BIT(16) /* F7 */
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#define USART_SR_CMF BIT(17) /* F7 */
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#define USART_SR_SBKF BIT(18) /* F7 */
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#define USART_SR_TEACK BIT(21) /* F7 */
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#define USART_SR_ERR_MASK (USART_SR_LBD | USART_SR_ORE | \
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USART_SR_FE | USART_SR_PE)
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/* Dummy bits */
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@ -64,7 +132,7 @@
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/* USART_CR1 */
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#define USART_CR1_SBK BIT(0)
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#define USART_CR1_RWU BIT(1)
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#define USART_CR1_RWU BIT(1) /* F4 */
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#define USART_CR1_RE BIT(2)
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#define USART_CR1_TE BIT(3)
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#define USART_CR1_IDLEIE BIT(4)
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@ -76,12 +144,20 @@
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#define USART_CR1_PCE BIT(10)
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#define USART_CR1_WAKE BIT(11)
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#define USART_CR1_M BIT(12)
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#define USART_CR1_UE BIT(13)
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#define USART_CR1_M0 BIT(12) /* F7 */
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#define USART_CR1_MME BIT(13) /* F7 */
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#define USART_CR1_CMIE BIT(14) /* F7 */
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#define USART_CR1_OVER8 BIT(15)
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#define USART_CR1_IE_MASK GENMASK(8, 4)
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#define USART_CR1_DEDT_MASK GENMASK(20, 16) /* F7 */
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#define USART_CR1_DEAT_MASK GENMASK(25, 21) /* F7 */
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#define USART_CR1_RTOIE BIT(26) /* F7 */
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#define USART_CR1_EOBIE BIT(27) /* F7 */
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#define USART_CR1_M1 BIT(28) /* F7 */
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#define USART_CR1_IE_MASK (GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27))
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/* USART_CR2 */
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#define USART_CR2_ADD_MASK GENMASK(3, 0)
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#define USART_CR2_ADD_MASK GENMASK(3, 0) /* F4 */
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#define USART_CR2_ADDM7 BIT(4) /* F7 */
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#define USART_CR2_LBDL BIT(5)
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#define USART_CR2_LBDIE BIT(6)
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#define USART_CR2_LBCL BIT(8)
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@ -91,6 +167,15 @@
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#define USART_CR2_STOP_2B BIT(13)
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#define USART_CR2_STOP_MASK GENMASK(13, 12)
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#define USART_CR2_LINEN BIT(14)
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#define USART_CR2_SWAP BIT(15) /* F7 */
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#define USART_CR2_RXINV BIT(16) /* F7 */
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#define USART_CR2_TXINV BIT(17) /* F7 */
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#define USART_CR2_DATAINV BIT(18) /* F7 */
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#define USART_CR2_MSBFIRST BIT(19) /* F7 */
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#define USART_CR2_ABREN BIT(20) /* F7 */
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#define USART_CR2_ABRMOD_MASK GENMASK(22, 21) /* F7 */
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#define USART_CR2_RTOEN BIT(23) /* F7 */
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#define USART_CR2_ADD_F7_MASK GENMASK(31, 24) /* F7 */
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/* USART_CR3 */
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#define USART_CR3_EIE BIT(0)
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@ -105,18 +190,47 @@
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#define USART_CR3_CTSE BIT(9)
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#define USART_CR3_CTSIE BIT(10)
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#define USART_CR3_ONEBIT BIT(11)
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#define USART_CR3_OVRDIS BIT(12) /* F7 */
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#define USART_CR3_DDRE BIT(13) /* F7 */
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#define USART_CR3_DEM BIT(14) /* F7 */
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#define USART_CR3_DEP BIT(15) /* F7 */
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#define USART_CR3_SCARCNT_MASK GENMASK(19, 17) /* F7 */
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/* USART_GTPR */
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#define USART_GTPR_PSC_MASK GENMASK(7, 0)
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#define USART_GTPR_GT_MASK GENMASK(15, 8)
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#define DRIVER_NAME "stm32-usart"
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/* USART_RTOR */
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#define USART_RTOR_RTO_MASK GENMASK(23, 0) /* F7 */
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#define USART_RTOR_BLEN_MASK GENMASK(31, 24) /* F7 */
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/* USART_RQR */
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#define USART_RQR_ABRRQ BIT(0) /* F7 */
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#define USART_RQR_SBKRQ BIT(1) /* F7 */
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#define USART_RQR_MMRQ BIT(2) /* F7 */
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#define USART_RQR_RXFRQ BIT(3) /* F7 */
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#define USART_RQR_TXFRQ BIT(4) /* F7 */
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/* USART_ICR */
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#define USART_ICR_PECF BIT(0) /* F7 */
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#define USART_ICR_FFECF BIT(1) /* F7 */
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#define USART_ICR_NCF BIT(2) /* F7 */
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#define USART_ICR_ORECF BIT(3) /* F7 */
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#define USART_ICR_IDLECF BIT(4) /* F7 */
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#define USART_ICR_TCCF BIT(6) /* F7 */
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#define USART_ICR_LBDCF BIT(8) /* F7 */
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#define USART_ICR_CTSCF BIT(9) /* F7 */
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#define USART_ICR_RTOCF BIT(11) /* F7 */
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#define USART_ICR_EOBCF BIT(12) /* F7 */
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#define USART_ICR_CMCF BIT(17) /* F7 */
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#define STM32_SERIAL_NAME "ttyS"
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#define STM32_MAX_PORTS 6
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struct stm32_port {
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struct uart_port port;
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struct clk *clk;
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struct stm32_usart_info *info;
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bool hw_flow_control;
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};
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@ -151,6 +265,8 @@ static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
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static void stm32_receive_chars(struct uart_port *port)
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{
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struct tty_port *tport = &port->state->port;
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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unsigned long c;
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u32 sr;
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char flag;
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@ -158,9 +274,9 @@ static void stm32_receive_chars(struct uart_port *port)
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if (port->irq_wake)
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pm_wakeup_event(tport->tty->dev, 0);
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while ((sr = readl_relaxed(port->membase + USART_SR)) & USART_SR_RXNE) {
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while ((sr = readl_relaxed(port->membase + ofs->isr)) & USART_SR_RXNE) {
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sr |= USART_SR_DUMMY_RX;
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c = readl_relaxed(port->membase + USART_DR);
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c = readl_relaxed(port->membase + ofs->rdr);
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flag = TTY_NORMAL;
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port->icount.rx++;
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@ -170,6 +286,10 @@ static void stm32_receive_chars(struct uart_port *port)
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if (uart_handle_break(port))
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continue;
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} else if (sr & USART_SR_ORE) {
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if (ofs->icr != UNDEF_REG)
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writel_relaxed(USART_ICR_ORECF,
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port->membase +
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ofs->icr);
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port->icount.overrun++;
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} else if (sr & USART_SR_PE) {
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port->icount.parity++;
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@ -199,10 +319,12 @@ static void stm32_receive_chars(struct uart_port *port)
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static void stm32_transmit_chars(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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struct circ_buf *xmit = &port->state->xmit;
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if (port->x_char) {
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writel_relaxed(port->x_char, port->membase + USART_DR);
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writel_relaxed(port->x_char, port->membase + ofs->tdr);
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port->x_char = 0;
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port->icount.tx++;
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return;
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@ -218,7 +340,7 @@ static void stm32_transmit_chars(struct uart_port *port)
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return;
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}
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writel_relaxed(xmit->buf[xmit->tail], port->membase + USART_DR);
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writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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@ -232,11 +354,13 @@ static void stm32_transmit_chars(struct uart_port *port)
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static irqreturn_t stm32_interrupt(int irq, void *ptr)
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{
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struct uart_port *port = ptr;
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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u32 sr;
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spin_lock(&port->lock);
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sr = readl_relaxed(port->membase + USART_SR);
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sr = readl_relaxed(port->membase + ofs->isr);
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if (sr & USART_SR_RXNE)
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stm32_receive_chars(port);
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@ -251,15 +375,21 @@ static irqreturn_t stm32_interrupt(int irq, void *ptr)
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static unsigned int stm32_tx_empty(struct uart_port *port)
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{
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return readl_relaxed(port->membase + USART_SR) & USART_SR_TXE;
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
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}
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static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
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stm32_set_bits(port, USART_CR3, USART_CR3_RTSE);
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stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
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else
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stm32_clr_bits(port, USART_CR3, USART_CR3_RTSE);
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stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
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}
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static unsigned int stm32_get_mctrl(struct uart_port *port)
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@ -271,44 +401,56 @@ static unsigned int stm32_get_mctrl(struct uart_port *port)
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/* Transmit stop */
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static void stm32_stop_tx(struct uart_port *port)
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{
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stm32_clr_bits(port, USART_CR1, USART_CR1_TXEIE);
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
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}
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/* There are probably characters waiting to be transmitted. */
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static void stm32_start_tx(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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struct circ_buf *xmit = &port->state->xmit;
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if (uart_circ_empty(xmit))
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return;
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stm32_set_bits(port, USART_CR1, USART_CR1_TXEIE | USART_CR1_TE);
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stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE | USART_CR1_TE);
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}
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/* Throttle the remote when input buffer is about to overflow. */
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static void stm32_throttle(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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unsigned long flags;
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spin_lock_irqsave(&port->lock, flags);
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stm32_clr_bits(port, USART_CR1, USART_CR1_RXNEIE);
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stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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/* Unthrottle the remote, the input buffer can now accept data. */
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static void stm32_unthrottle(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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unsigned long flags;
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spin_lock_irqsave(&port->lock, flags);
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stm32_set_bits(port, USART_CR1, USART_CR1_RXNEIE);
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stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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/* Receive stop */
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static void stm32_stop_rx(struct uart_port *port)
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{
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stm32_clr_bits(port, USART_CR1, USART_CR1_RXNEIE);
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
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}
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/* Handle breaks - ignored by us */
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@ -318,6 +460,8 @@ static void stm32_break_ctl(struct uart_port *port, int break_state)
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static int stm32_startup(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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const char *name = to_platform_device(port->dev)->name;
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u32 val;
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int ret;
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@ -327,17 +471,19 @@ static int stm32_startup(struct uart_port *port)
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return ret;
|
||||
|
||||
val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
|
||||
stm32_set_bits(port, USART_CR1, val);
|
||||
stm32_set_bits(port, ofs->cr1, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void stm32_shutdown(struct uart_port *port)
|
||||
{
|
||||
struct stm32_port *stm32_port = to_stm32_port(port);
|
||||
struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
|
||||
u32 val;
|
||||
|
||||
val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
|
||||
stm32_set_bits(port, USART_CR1, val);
|
||||
stm32_set_bits(port, ofs->cr1, val);
|
||||
|
||||
free_irq(port->irq, port);
|
||||
}
|
||||
|
|
@ -346,6 +492,8 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
|
|||
struct ktermios *old)
|
||||
{
|
||||
struct stm32_port *stm32_port = to_stm32_port(port);
|
||||
struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
|
||||
struct stm32_usart_config *cfg = &stm32_port->info->cfg;
|
||||
unsigned int baud;
|
||||
u32 usartdiv, mantissa, fraction, oversampling;
|
||||
tcflag_t cflag = termios->c_cflag;
|
||||
|
|
@ -360,9 +508,10 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
|
|||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
/* Stop serial port and reset value */
|
||||
writel_relaxed(0, port->membase + USART_CR1);
|
||||
writel_relaxed(0, port->membase + ofs->cr1);
|
||||
|
||||
cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE | USART_CR1_RXNEIE;
|
||||
cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
|
||||
cr1 |= BIT(cfg->uart_enable_bit);
|
||||
cr2 = 0;
|
||||
cr3 = 0;
|
||||
|
||||
|
|
@ -371,8 +520,12 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
|
|||
|
||||
if (cflag & PARENB) {
|
||||
cr1 |= USART_CR1_PCE;
|
||||
if ((cflag & CSIZE) == CS8)
|
||||
cr1 |= USART_CR1_M;
|
||||
if ((cflag & CSIZE) == CS8) {
|
||||
if (cfg->has_7bits_data)
|
||||
cr1 |= USART_CR1_M0;
|
||||
else
|
||||
cr1 |= USART_CR1_M;
|
||||
}
|
||||
}
|
||||
|
||||
if (cflag & PARODD)
|
||||
|
|
@ -394,15 +547,15 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
|
|||
*/
|
||||
if (usartdiv < 16) {
|
||||
oversampling = 8;
|
||||
stm32_set_bits(port, USART_CR1, USART_CR1_OVER8);
|
||||
stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
|
||||
} else {
|
||||
oversampling = 16;
|
||||
stm32_clr_bits(port, USART_CR1, USART_CR1_OVER8);
|
||||
stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
|
||||
}
|
||||
|
||||
mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
|
||||
fraction = usartdiv % oversampling;
|
||||
writel_relaxed(mantissa | fraction, port->membase + USART_BRR);
|
||||
writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
|
||||
|
||||
uart_update_timeout(port, cflag, baud);
|
||||
|
||||
|
|
@ -430,9 +583,9 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
|
|||
if ((termios->c_cflag & CREAD) == 0)
|
||||
port->ignore_status_mask |= USART_SR_DUMMY_RX;
|
||||
|
||||
writel_relaxed(cr3, port->membase + USART_CR3);
|
||||
writel_relaxed(cr2, port->membase + USART_CR2);
|
||||
writel_relaxed(cr1, port->membase + USART_CR1);
|
||||
writel_relaxed(cr3, port->membase + ofs->cr3);
|
||||
writel_relaxed(cr2, port->membase + ofs->cr2);
|
||||
writel_relaxed(cr1, port->membase + ofs->cr1);
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
}
|
||||
|
|
@ -469,6 +622,8 @@ static void stm32_pm(struct uart_port *port, unsigned int state,
|
|||
{
|
||||
struct stm32_port *stm32port = container_of(port,
|
||||
struct stm32_port, port);
|
||||
struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
|
||||
struct stm32_usart_config *cfg = &stm32port->info->cfg;
|
||||
unsigned long flags = 0;
|
||||
|
||||
switch (state) {
|
||||
|
|
@ -477,7 +632,7 @@ static void stm32_pm(struct uart_port *port, unsigned int state,
|
|||
break;
|
||||
case UART_PM_STATE_OFF:
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
stm32_clr_bits(port, USART_CR1, USART_CR1_UE);
|
||||
stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
clk_disable_unprepare(stm32port->clk);
|
||||
break;
|
||||
|
|
@ -567,8 +722,10 @@ static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
|
|||
|
||||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id stm32_match[] = {
|
||||
{ .compatible = "st,stm32-usart", },
|
||||
{ .compatible = "st,stm32-uart", },
|
||||
{ .compatible = "st,stm32-usart", .data = &stm32f4_info},
|
||||
{ .compatible = "st,stm32-uart", .data = &stm32f4_info},
|
||||
{ .compatible = "st,stm32f7-usart", .data = &stm32f7_info},
|
||||
{ .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
|
||||
{},
|
||||
};
|
||||
|
||||
|
|
@ -577,13 +734,20 @@ MODULE_DEVICE_TABLE(of, stm32_match);
|
|||
|
||||
static int stm32_serial_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
const struct of_device_id *match;
|
||||
struct stm32_port *stm32port;
|
||||
int ret;
|
||||
|
||||
stm32port = stm32_of_get_stm32_port(pdev);
|
||||
if (!stm32port)
|
||||
return -ENODEV;
|
||||
|
||||
match = of_match_device(stm32_match, &pdev->dev);
|
||||
if (match && match->data)
|
||||
stm32port->info = (struct stm32_usart_info *)match->data;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
ret = stm32_init_port(stm32port, pdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -608,15 +772,20 @@ static int stm32_serial_remove(struct platform_device *pdev)
|
|||
#ifdef CONFIG_SERIAL_STM32_CONSOLE
|
||||
static void stm32_console_putchar(struct uart_port *port, int ch)
|
||||
{
|
||||
while (!(readl_relaxed(port->membase + USART_SR) & USART_SR_TXE))
|
||||
struct stm32_port *stm32_port = to_stm32_port(port);
|
||||
struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
|
||||
|
||||
while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
|
||||
cpu_relax();
|
||||
|
||||
writel_relaxed(ch, port->membase + USART_DR);
|
||||
writel_relaxed(ch, port->membase + ofs->tdr);
|
||||
}
|
||||
|
||||
static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
|
||||
{
|
||||
struct uart_port *port = &stm32_ports[co->index].port;
|
||||
struct stm32_port *stm32_port = to_stm32_port(port);
|
||||
struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
|
||||
unsigned long flags;
|
||||
u32 old_cr1, new_cr1;
|
||||
int locked = 1;
|
||||
|
|
@ -630,14 +799,14 @@ static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
|
|||
spin_lock(&port->lock);
|
||||
|
||||
/* Save and disable interrupts */
|
||||
old_cr1 = readl_relaxed(port->membase + USART_CR1);
|
||||
old_cr1 = readl_relaxed(port->membase + ofs->cr1);
|
||||
new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
|
||||
writel_relaxed(new_cr1, port->membase + USART_CR1);
|
||||
writel_relaxed(new_cr1, port->membase + ofs->cr1);
|
||||
|
||||
uart_console_write(port, s, cnt, stm32_console_putchar);
|
||||
|
||||
/* Restore interrupt state */
|
||||
writel_relaxed(old_cr1, port->membase + USART_CR1);
|
||||
writel_relaxed(old_cr1, port->membase + ofs->cr1);
|
||||
|
||||
if (locked)
|
||||
spin_unlock(&port->lock);
|
||||
|
|
|
|||
Loading…
Reference in New Issue