This cleans up the ks8695 timer driver and converts
it to use generic time and clock events. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iQIcBAABAgAGBQJQRwjGAAoJEEEQszewGV1zRaQP/i+htTsjDmRp5/U0xEV4dSUQ 6GLZCK7s2GpU4U3jGrDQxFSuLcPteo4yu8AO3V2GGcrVrgSpkjnyitMKLz2HbDBG KGj0QH3jofYyecxZjaqZs3ytJRsgoH5YvVI6BmOf4lYr6k606SfDtzYJ5EikpzSQ k59QvIsLcePIbBF+sOrgsjWbToA/bsYAsfijpq/PmysiMq84yEq7atHnUW1WmeSs 87iguNBGuJ231dI1vn8rl9IMm1nLqh7m0BEND+vmgoOhWq0bkYn7BOmEomudVIhH iX2sv0tT5X50QrJ3THBH0pWNwpe+gICMhgiQI5qEfLRk2lKvqYRhXONY/fP6BrK8 mxZqVKE9bqUXRCytG5kARTtKVenbriFT22HBIF79eDK+gvHZqAEYJEz78sd6/rG9 UK5NS3k8TvJhBMmKoKp+SHZ7br8VF81B5z90v0KR5M2YvpZIPVmc0UmUZs2mZv2V +qU8SccDnnchc6rH+EIIEwfu/zqZgCyOofwFy0KpFUuwHVBRhDZ9Psi9SE2kkrH+ Yk9bRxdcSOwmu5+dcGvj0ljagM98L/ahp5Ki8bfGhAIaQKTDuvs/RBUQnV1STLXk JAJGouXwRFJwcA+R73ezuUO41FEgqEVdYmN0XdjOnTRTa5B7ofEFHPsn2pJ/9xbT r+W/eookaudoPAAGpm97 =6GPY -----END PGP SIGNATURE----- Merge tag 'ks8695-time-for-arm-soc' of http://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/cleanup This cleans up the ks8695 timer driver and converts it to use generic time and clock events. * tag 'ks8695-time-for-arm-soc' of http://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: ARM: ks8695: convert to generic time and clocksource ARM: ks8695: delete resume hook from timer ARM: ks8695: use [readl|writel]_relaxed() ARM: ks8695: merge the timer header into the timer driverhifive-unleashed-5.1
Olof Johansson
commit
ae2fe0c0ca
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@ -641,8 +641,9 @@ config ARCH_KS8695
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bool "Micrel/Kendin KS8695"
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select CPU_ARM922T
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select ARCH_REQUIRE_GPIOLIB
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select ARCH_USES_GETTIMEOFFSET
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select NEED_MACH_MEMORY_H
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select CLKSRC_MMIO
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select GENERIC_CLOCKEVENTS
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help
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Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
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System-on-Chip devices.
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@ -1,40 +0,0 @@
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/*
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* arch/arm/mach-ks8695/include/mach/regs-timer.h
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*
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* Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
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* Copyright (C) 2006 Simtec Electronics
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*
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* KS8695 - Timer registers and bit definitions.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef KS8695_TIMER_H
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#define KS8695_TIMER_H
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#define KS8695_TMR_OFFSET (0xF0000 + 0xE400)
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#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET)
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#define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET)
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/*
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* Timer registers
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*/
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#define KS8695_TMCON (0x00) /* Timer Control Register */
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#define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */
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#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */
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#define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */
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#define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */
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/* Timer Control Register */
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#define TMCON_T1EN (1 << 1) /* Timer 1 Enable */
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#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */
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/* Timer0 Timeout Counter Register */
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#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */
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#endif
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@ -25,53 +25,98 @@
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/io.h>
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#include <linux/clockchips.h>
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#include <asm/mach/time.h>
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#include <asm/system_misc.h>
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#include <mach/regs-timer.h>
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#include <mach/regs-irq.h>
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#include "generic.h"
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#define KS8695_TMR_OFFSET (0xF0000 + 0xE400)
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#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET)
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#define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET)
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/*
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* Returns number of ms since last clock interrupt. Note that interrupts
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* will have been disabled by do_gettimeoffset()
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* Timer registers
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*/
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static unsigned long ks8695_gettimeoffset (void)
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#define KS8695_TMCON (0x00) /* Timer Control Register */
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#define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */
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#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */
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#define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */
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#define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */
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/* Timer Control Register */
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#define TMCON_T1EN (1 << 1) /* Timer 1 Enable */
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#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */
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/* Timer0 Timeout Counter Register */
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#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */
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static void ks8695_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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unsigned long elapsed, tick2, intpending;
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u32 tmcon;
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/*
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* Get the current number of ticks. Note that there is a race
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* condition between us reading the timer and checking for an
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* interrupt. We solve this by ensuring that the counter has not
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* reloaded between our two reads.
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*/
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elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD);
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do {
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tick2 = elapsed;
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intpending = __raw_readl(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1);
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elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD);
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} while (elapsed > tick2);
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if (mode == CLOCK_EVT_FEAT_PERIODIC) {
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u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ);
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u32 half = DIV_ROUND_CLOSEST(rate, 2);
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/* Convert to number of ticks expired (not remaining) */
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elapsed = (CLOCK_TICK_RATE / HZ) - elapsed;
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/* Disable timer 1 */
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tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
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tmcon &= ~TMCON_T1EN;
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writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
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/* Is interrupt pending? If so, then timer has been reloaded already. */
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if (intpending)
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elapsed += (CLOCK_TICK_RATE / HZ);
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/* Both registers need to count down */
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writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
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writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
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/* Convert ticks to usecs */
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return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH;
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/* Re-enable timer1 */
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tmcon |= TMCON_T1EN;
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writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
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}
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}
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static int ks8695_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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u32 half = DIV_ROUND_CLOSEST(cycles, 2);
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u32 tmcon;
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/* Disable timer 1 */
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tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
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tmcon &= ~TMCON_T1EN;
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writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
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/* Both registers need to count down */
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writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
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writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
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/* Re-enable timer1 */
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tmcon |= TMCON_T1EN;
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writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
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return 0;
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}
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static struct clock_event_device clockevent_ks8695 = {
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.name = "ks8695_t1tc",
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.rating = 300, /* Reasonably fast and accurate clock event */
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
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.set_next_event = ks8695_set_next_event,
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.set_mode = ks8695_set_mode,
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};
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/*
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* IRQ handler for the timer.
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*/
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static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id)
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{
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timer_tick();
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struct clock_event_device *evt = &clockevent_ks8695;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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@ -83,18 +128,22 @@ static struct irqaction ks8695_timer_irq = {
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static void ks8695_timer_setup(void)
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{
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unsigned long tmout = CLOCK_TICK_RATE / HZ;
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unsigned long tmcon;
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/* disable timer1 */
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tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
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__raw_writel(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
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/* Disable timer 0 and 1 */
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tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
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tmcon &= ~TMCON_T0EN;
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tmcon &= ~TMCON_T1EN;
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writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
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__raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1TC);
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__raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1PD);
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/* re-enable timer1 */
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__raw_writel(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
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/*
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* Use timer 1 to fire IRQs on the timeline, minimum 2 cycles
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* (one on each counter) maximum 2*2^32, but the API will only
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* accept up to a 32bit full word (0xFFFFFFFFU).
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*/
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clockevents_config_and_register(&clockevent_ks8695,
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KS8695_CLOCK_RATE, 2,
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0xFFFFFFFFU);
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}
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static void __init ks8695_timer_init (void)
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@ -107,8 +156,6 @@ static void __init ks8695_timer_init (void)
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struct sys_timer ks8695_timer = {
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.init = ks8695_timer_init,
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.offset = ks8695_gettimeoffset,
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.resume = ks8695_timer_setup,
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};
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void ks8695_restart(char mode, const char *cmd)
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@ -119,12 +166,12 @@ void ks8695_restart(char mode, const char *cmd)
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soft_restart(0);
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/* disable timer0 */
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reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
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__raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
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reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
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writel_relaxed(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
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/* enable watchdog mode */
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__raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
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writel_relaxed((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
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/* re-enable timer0 */
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__raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
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writel_relaxed(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
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}
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