perf/x86/intel: Fix SLM MSR_OFFCORE_RSP1 valid_mask
AVG_LATENCY(bit 38) is only available on MSR_OFFCORE_RSP0. So the bit should be removed from RSP1 valid_mask. Since RSP0 and RSP1 may have different valid_mask, intel_alt_er should validate the config on the alternate offcore reg before replacing it. Signed-off-by: Kan Liang <kan.liang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1435170215-5017-1-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -1114,7 +1114,7 @@ static struct extra_reg intel_slm_extra_regs[] __read_mostly =
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{
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/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
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INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
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INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x768005ffffull, RSP_1),
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INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
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EVENT_EXTRA_END
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};
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@ -1699,18 +1699,22 @@ intel_bts_constraints(struct perf_event *event)
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return NULL;
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}
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static int intel_alt_er(int idx)
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static int intel_alt_er(int idx, u64 config)
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{
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int alt_idx;
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if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
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return idx;
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if (idx == EXTRA_REG_RSP_0)
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return EXTRA_REG_RSP_1;
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alt_idx = EXTRA_REG_RSP_1;
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if (idx == EXTRA_REG_RSP_1)
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return EXTRA_REG_RSP_0;
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alt_idx = EXTRA_REG_RSP_0;
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return idx;
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if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
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return idx;
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return alt_idx;
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}
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static void intel_fixup_er(struct perf_event *event, int idx)
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@ -1799,7 +1803,7 @@ again:
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*/
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c = NULL;
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} else {
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idx = intel_alt_er(idx);
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idx = intel_alt_er(idx, reg->config);
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if (idx != reg->idx) {
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raw_spin_unlock_irqrestore(&era->lock, flags);
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goto again;
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