drm/amd/display: Fix setting DP_VID_N_MUL
[Why] Need to set VID_N_MUL for 4:2:0 cases [How] Move setting to enc1_stream_encoder_dp_unblank and ensure it is also set for non-4:2:0 cases. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1054,6 +1054,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
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/* only 3 items below are used by unblank */
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/* only 3 items below are used by unblank */
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params.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
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params.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
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params.link_settings.link_rate = link_settings->link_rate;
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params.link_settings.link_rate = link_settings->link_rate;
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params.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
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if (dc_is_dp_signal(pipe_ctx->stream->signal))
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if (dc_is_dp_signal(pipe_ctx->stream->signal))
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pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms);
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pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms);
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@ -298,7 +298,6 @@ void enc1_stream_encoder_dp_set_stream_attribute(
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break;
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break;
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case PIXEL_ENCODING_YCBCR420:
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case PIXEL_ENCODING_YCBCR420:
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dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420;
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dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420;
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REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
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break;
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break;
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default:
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default:
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dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444;
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dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444;
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@ -833,13 +832,17 @@ void enc1_stream_encoder_dp_unblank(
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if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
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if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
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uint32_t n_vid = 0x8000;
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uint32_t n_vid = 0x8000;
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uint32_t m_vid;
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uint32_t m_vid;
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uint32_t n_multiply = 0;
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uint64_t m_vid_l = n_vid;
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/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
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if (param->pixel_encoding == PIXEL_ENCODING_YCBCR420)
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n_multiply = 1;
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/* M / N = Fstream / Flink
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/* M / N = Fstream / Flink
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* m_vid / n_vid = pixel rate / link rate
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* m_vid / n_vid = pixel rate / link rate
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*/
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*/
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uint64_t m_vid_l = n_vid;
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m_vid_l *= param->pixel_clk_khz;
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m_vid_l *= param->pixel_clk_khz;
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m_vid_l = div_u64(m_vid_l,
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m_vid_l = div_u64(m_vid_l,
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param->link_settings.link_rate
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param->link_settings.link_rate
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@ -859,7 +862,9 @@ void enc1_stream_encoder_dp_unblank(
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REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
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REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
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REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
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REG_UPDATE_2(DP_VID_TIMING,
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DP_VID_M_N_GEN_EN, 1,
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DP_VID_N_MUL, n_multiply);
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}
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}
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/* set DIG_START to 0x1 to resync FIFO */
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/* set DIG_START to 0x1 to resync FIFO */
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@ -68,6 +68,7 @@ struct encoder_info_frame {
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struct encoder_unblank_param {
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struct encoder_unblank_param {
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struct dc_link_settings link_settings;
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struct dc_link_settings link_settings;
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unsigned int pixel_clk_khz;
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unsigned int pixel_clk_khz;
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enum dc_pixel_encoding pixel_encoding;
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};
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};
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struct encoder_set_dp_phy_pattern_param {
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struct encoder_set_dp_phy_pattern_param {
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