Staging: et131x: clean up MAC_STAT register
One by one... Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Alan Cox
Greg Kroah-Hartman
parent
b491f147a1
commit
ae8d9d845a
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@ -1577,120 +1577,60 @@ typedef struct _MAC_t { /* Location: */
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/*
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* structure for Carry Register One and it's Mask Register reg located in mac
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* stat address map address 0x6130 and 0x6138.
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*
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* 31: tr64
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* 30: tr127
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* 29: tr255
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* 28: tr511
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* 27: tr1k
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* 26: trmax
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* 25: trmgv
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* 24-17: unused
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* 16: rbyt
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* 15: rpkt
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* 14: rfcs
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* 13: rmca
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* 12: rbca
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* 11: rxcf
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* 10: rxpf
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* 9: rxuo
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* 8: raln
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* 7: rflr
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* 6: rcde
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* 5: rcse
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* 4: rund
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* 3: rovr
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* 2: rfrg
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* 1: rjbr
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* 0: rdrp
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*/
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typedef union _MAC_STAT_REG_1_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 tr64:1; /* bit 31 */
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u32 tr127:1; /* bit 30 */
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u32 tr255:1; /* bit 29 */
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u32 tr511:1; /* bit 28 */
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u32 tr1k:1; /* bit 27 */
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u32 trmax:1; /* bit 26 */
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u32 trmgv:1; /* bit 25 */
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u32 unused:8; /* bits 17-24 */
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u32 rbyt:1; /* bit 16 */
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u32 rpkt:1; /* bit 15 */
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u32 rfcs:1; /* bit 14 */
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u32 rmca:1; /* bit 13 */
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u32 rbca:1; /* bit 12 */
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u32 rxcf:1; /* bit 11 */
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u32 rxpf:1; /* bit 10 */
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u32 rxuo:1; /* bit 9 */
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u32 raln:1; /* bit 8 */
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u32 rflr:1; /* bit 7 */
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u32 rcde:1; /* bit 6 */
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u32 rcse:1; /* bit 5 */
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u32 rund:1; /* bit 4 */
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u32 rovr:1; /* bit 3 */
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u32 rfrg:1; /* bit 2 */
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u32 rjbr:1; /* bit 1 */
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u32 rdrp:1; /* bit 0 */
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#else
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u32 rdrp:1; /* bit 0 */
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u32 rjbr:1; /* bit 1 */
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u32 rfrg:1; /* bit 2 */
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u32 rovr:1; /* bit 3 */
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u32 rund:1; /* bit 4 */
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u32 rcse:1; /* bit 5 */
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u32 rcde:1; /* bit 6 */
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u32 rflr:1; /* bit 7 */
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u32 raln:1; /* bit 8 */
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u32 rxuo:1; /* bit 9 */
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u32 rxpf:1; /* bit 10 */
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u32 rxcf:1; /* bit 11 */
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u32 rbca:1; /* bit 12 */
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u32 rmca:1; /* bit 13 */
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u32 rfcs:1; /* bit 14 */
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u32 rpkt:1; /* bit 15 */
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u32 rbyt:1; /* bit 16 */
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u32 unused:8; /* bits 17-24 */
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u32 trmgv:1; /* bit 25 */
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u32 trmax:1; /* bit 26 */
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u32 tr1k:1; /* bit 27 */
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u32 tr511:1; /* bit 28 */
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u32 tr255:1; /* bit 29 */
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u32 tr127:1; /* bit 30 */
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u32 tr64:1; /* bit 31 */
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#endif
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} bits;
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} MAC_STAT_REG_1_t, *PMAC_STAT_REG_1_t;
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/*
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* structure for Carry Register Two Mask Register reg in mac stat address map.
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* located at address 0x613C
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*
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* 31-20: unused
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* 19: tjbr
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* 18: tfcs
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* 17: txcf
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* 16: tovr
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* 15: tund
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* 14: trfg
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* 13: tbyt
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* 12: tpkt
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* 11: tmca
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* 10: tbca
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* 9: txpf
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* 8: tdfr
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* 7: tedf
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* 6: tscl
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* 5: tmcl
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* 4: tlcl
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* 3: txcl
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* 2: tncl
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* 1: tpfh
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* 0: tdrp
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*/
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typedef union _MAC_STAT_REG_2_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 unused:12; /* bit 20-31 */
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u32 tjbr:1; /* bit 19 */
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u32 tfcs:1; /* bit 18 */
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u32 txcf:1; /* bit 17 */
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u32 tovr:1; /* bit 16 */
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u32 tund:1; /* bit 15 */
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u32 tfrg:1; /* bit 14 */
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u32 tbyt:1; /* bit 13 */
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u32 tpkt:1; /* bit 12 */
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u32 tmca:1; /* bit 11 */
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u32 tbca:1; /* bit 10 */
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u32 txpf:1; /* bit 9 */
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u32 tdfr:1; /* bit 8 */
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u32 tedf:1; /* bit 7 */
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u32 tscl:1; /* bit 6 */
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u32 tmcl:1; /* bit 5 */
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u32 tlcl:1; /* bit 4 */
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u32 txcl:1; /* bit 3 */
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u32 tncl:1; /* bit 2 */
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u32 tpfh:1; /* bit 1 */
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u32 tdrp:1; /* bit 0 */
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#else
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u32 tdrp:1; /* bit 0 */
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u32 tpfh:1; /* bit 1 */
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u32 tncl:1; /* bit 2 */
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u32 txcl:1; /* bit 3 */
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u32 tlcl:1; /* bit 4 */
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u32 tmcl:1; /* bit 5 */
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u32 tscl:1; /* bit 6 */
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u32 tedf:1; /* bit 7 */
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u32 tdfr:1; /* bit 8 */
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u32 txpf:1; /* bit 9 */
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u32 tbca:1; /* bit 10 */
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u32 tmca:1; /* bit 11 */
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u32 tpkt:1; /* bit 12 */
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u32 tbyt:1; /* bit 13 */
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u32 tfrg:1; /* bit 14 */
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u32 tund:1; /* bit 15 */
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u32 tovr:1; /* bit 16 */
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u32 txcf:1; /* bit 17 */
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u32 tfcs:1; /* bit 18 */
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u32 tjbr:1; /* bit 19 */
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u32 unused:12; /* bit 20-31 */
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#endif
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} bits;
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} MAC_STAT_REG_2_t, *PMAC_STAT_REG_2_t;
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/*
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* MAC STATS Module of JAGCore Address Mapping
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@ -1831,16 +1771,16 @@ typedef struct _MAC_STAT_t { /* Location: */
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u32 TFrg; /* 0x612C */
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/* Carry Register One Register */
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MAC_STAT_REG_1_t Carry1; /* 0x6130 */
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u32 Carry1; /* 0x6130 */
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/* Carry Register Two Register */
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MAC_STAT_REG_2_t Carry2; /* 0x6134 */
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u32 Carry2; /* 0x6134 */
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/* Carry Register One Mask Register */
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MAC_STAT_REG_1_t Carry1M; /* 0x6138 */
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u32 Carry1M; /* 0x6138 */
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/* Carry Register Two Mask Register */
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MAC_STAT_REG_2_t Carry2M; /* 0x613C */
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u32 Carry2M; /* 0x613C */
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} MAC_STAT_t, *PMAC_STAT_t;
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/* END OF MAC STAT REGISTER ADDRESS MAP */
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@ -414,63 +414,8 @@ void ConfigMacStatRegs(struct et131x_adapter *etdev)
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* Initially this will be all counters. It may become clear later
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* that we do not need to track all counters.
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*/
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{
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MAC_STAT_REG_1_t Carry1M = { 0xffffffff };
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Carry1M.bits.rdrp = 0;
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Carry1M.bits.rjbr = 1;
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Carry1M.bits.rfrg = 0;
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Carry1M.bits.rovr = 0;
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Carry1M.bits.rund = 1;
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Carry1M.bits.rcse = 1;
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Carry1M.bits.rcde = 0;
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Carry1M.bits.rflr = 0;
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Carry1M.bits.raln = 0;
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Carry1M.bits.rxuo = 1;
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Carry1M.bits.rxpf = 1;
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Carry1M.bits.rxcf = 1;
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Carry1M.bits.rbca = 1;
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Carry1M.bits.rmca = 1;
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Carry1M.bits.rfcs = 0;
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Carry1M.bits.rpkt = 1;
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Carry1M.bits.rbyt = 1;
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Carry1M.bits.trmgv = 1;
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Carry1M.bits.trmax = 1;
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Carry1M.bits.tr1k = 1;
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Carry1M.bits.tr511 = 1;
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Carry1M.bits.tr255 = 1;
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Carry1M.bits.tr127 = 1;
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Carry1M.bits.tr64 = 1;
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writel(Carry1M.value, &pDevMacStat->Carry1M.value);
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}
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{
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MAC_STAT_REG_2_t Carry2M = { 0xffffffff };
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Carry2M.bits.tdrp = 1;
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Carry2M.bits.tpfh = 1;
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Carry2M.bits.tncl = 0;
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Carry2M.bits.txcl = 1;
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Carry2M.bits.tlcl = 0;
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Carry2M.bits.tmcl = 0;
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Carry2M.bits.tscl = 0;
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Carry2M.bits.tedf = 1;
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Carry2M.bits.tdfr = 0;
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Carry2M.bits.txpf = 1;
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Carry2M.bits.tbca = 1;
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Carry2M.bits.tmca = 1;
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Carry2M.bits.tpkt = 1;
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Carry2M.bits.tbyt = 1;
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Carry2M.bits.tfrg = 1;
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Carry2M.bits.tund = 0;
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Carry2M.bits.tovr = 0;
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Carry2M.bits.txcf = 1;
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Carry2M.bits.tfcs = 1;
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Carry2M.bits.tjbr = 1;
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writel(Carry2M.value, &pDevMacStat->Carry2M.value);
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}
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writel(0xFFFFBE32, &pDevMacStat->Carry1M);
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writel(0xFFFE7E8B, &pDevMacStat->Carry2M);
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}
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void ConfigFlowControl(struct et131x_adapter *etdev)
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@ -546,17 +491,17 @@ void UpdateMacStatHostCounters(struct et131x_adapter *etdev)
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*/
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void HandleMacStatInterrupt(struct et131x_adapter *etdev)
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{
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MAC_STAT_REG_1_t Carry1;
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MAC_STAT_REG_2_t Carry2;
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u32 Carry1;
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u32 Carry2;
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/* Read the interrupt bits from the register(s). These are Clear On
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* Write.
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*/
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Carry1.value = readl(&etdev->regs->macStat.Carry1.value);
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Carry2.value = readl(&etdev->regs->macStat.Carry2.value);
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Carry1 = readl(&etdev->regs->macStat.Carry1);
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Carry2 = readl(&etdev->regs->macStat.Carry2);
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writel(Carry1.value, &etdev->regs->macStat.Carry1.value);
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writel(Carry2.value, &etdev->regs->macStat.Carry2.value);
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writel(Carry1, &etdev->regs->macStat.Carry1);
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writel(Carry2, &etdev->regs->macStat.Carry2);
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/* We need to do update the host copy of all the MAC_STAT counters.
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* For each counter, check it's overflow bit. If the overflow bit is
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@ -564,33 +509,33 @@ void HandleMacStatInterrupt(struct et131x_adapter *etdev)
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* revolution of the counter. This routine is called when the counter
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* block indicates that one of the counters has wrapped.
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*/
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if (Carry1.bits.rfcs)
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if (Carry1 & (1 << 14))
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etdev->Stats.code_violations += COUNTER_WRAP_16_BIT;
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if (Carry1.bits.raln)
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if (Carry1 & (1 << 8))
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etdev->Stats.alignment_err += COUNTER_WRAP_12_BIT;
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if (Carry1.bits.rflr)
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if (Carry1 & (1 << 7))
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etdev->Stats.length_err += COUNTER_WRAP_16_BIT;
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if (Carry1.bits.rfrg)
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if (Carry1 & (1 << 2))
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etdev->Stats.other_errors += COUNTER_WRAP_16_BIT;
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if (Carry1.bits.rcde)
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if (Carry1 & (1 << 6))
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etdev->Stats.crc_err += COUNTER_WRAP_16_BIT;
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if (Carry1.bits.rovr)
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if (Carry1 & (1 << 3))
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etdev->Stats.rx_ov_flow += COUNTER_WRAP_16_BIT;
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if (Carry1.bits.rdrp)
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if (Carry1 & (1 << 0))
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etdev->Stats.norcvbuf += COUNTER_WRAP_16_BIT;
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if (Carry2.bits.tovr)
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if (Carry2 & (1 << 16))
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etdev->Stats.max_pkt_error += COUNTER_WRAP_12_BIT;
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if (Carry2.bits.tund)
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if (Carry2 & (1 << 15))
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etdev->Stats.tx_uflo += COUNTER_WRAP_12_BIT;
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if (Carry2.bits.tscl)
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if (Carry2 & (1 << 6))
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etdev->Stats.first_collision += COUNTER_WRAP_12_BIT;
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if (Carry2.bits.tdfr)
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if (Carry2 & (1 << 8))
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etdev->Stats.tx_deferred += COUNTER_WRAP_12_BIT;
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if (Carry2.bits.tmcl)
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if (Carry2 & (1 << 5))
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etdev->Stats.excessive_collisions += COUNTER_WRAP_12_BIT;
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if (Carry2.bits.tlcl)
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if (Carry2 & (1 << 4))
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etdev->Stats.late_collisions += COUNTER_WRAP_12_BIT;
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if (Carry2.bits.tncl)
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if (Carry2 & (1 << 2))
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etdev->Stats.collisions += COUNTER_WRAP_12_BIT;
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}
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