watchdog: add rza_wdt driver
Adds a watchdog timer driver for the Renesas RZ/A Series SoCs. A reset handler is also included since a WDT overflow is the only method for restarting an RZ/A SoC. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>hifive-unleashed-5.1
Chris Brandt
Wim Van Sebroeck
parent
5dca80f63e
commit
aea24187f6
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@ -721,6 +721,14 @@ config RENESAS_WDT
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This driver adds watchdog support for the integrated watchdogs in the
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Renesas R-Car and other SH-Mobile SoCs (usually named RWDT or SWDT).
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config RENESAS_RZAWDT
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tristate "Renesas RZ/A WDT Watchdog"
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depends on ARCH_RENESAS || COMPILE_TEST
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select WATCHDOG_CORE
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help
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This driver adds watchdog support for the integrated watchdogs in the
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Renesas RZ/A SoCs. These watchdogs can be used to reset a system.
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config ASPEED_WATCHDOG
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tristate "Aspeed 2400 watchdog support"
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depends on ARCH_ASPEED || COMPILE_TEST
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@ -82,6 +82,7 @@ obj-$(CONFIG_LPC18XX_WATCHDOG) += lpc18xx_wdt.o
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obj-$(CONFIG_BCM7038_WDT) += bcm7038_wdt.o
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obj-$(CONFIG_ATLAS7_WATCHDOG) += atlas7_wdt.o
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obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o
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obj-$(CONFIG_RENESAS_RZAWDT) += rza_wdt.o
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obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o
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obj-$(CONFIG_ZX2967_WATCHDOG) += zx2967_wdt.o
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@ -0,0 +1,199 @@
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/*
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* Renesas RZ/A Series WDT Driver
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*
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* Copyright (C) 2017 Renesas Electronics America, Inc.
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* Copyright (C) 2017 Chris Brandt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/watchdog.h>
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#define DEFAULT_TIMEOUT 30
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/* Watchdog Timer Registers */
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#define WTCSR 0
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#define WTCSR_MAGIC 0xA500
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#define WTSCR_WT BIT(6)
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#define WTSCR_TME BIT(5)
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#define WTSCR_CKS(i) (i)
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#define WTCNT 2
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#define WTCNT_MAGIC 0x5A00
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#define WRCSR 4
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#define WRCSR_MAGIC 0x5A00
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#define WRCSR_RSTE BIT(6)
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#define WRCSR_CLEAR_WOVF 0xA500 /* special value */
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struct rza_wdt {
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struct watchdog_device wdev;
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void __iomem *base;
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struct clk *clk;
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};
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static int rza_wdt_start(struct watchdog_device *wdev)
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{
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struct rza_wdt *priv = watchdog_get_drvdata(wdev);
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/* Stop timer */
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writew(WTCSR_MAGIC | 0, priv->base + WTCSR);
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/* Must dummy read WRCSR:WOVF at least once before clearing */
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readb(priv->base + WRCSR);
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writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR);
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/*
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* Start timer with slowest clock source and reset option enabled.
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*/
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writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR);
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writew(WTCNT_MAGIC | 0, priv->base + WTCNT);
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writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME | WTSCR_CKS(7),
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priv->base + WTCSR);
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return 0;
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}
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static int rza_wdt_stop(struct watchdog_device *wdev)
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{
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struct rza_wdt *priv = watchdog_get_drvdata(wdev);
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writew(WTCSR_MAGIC | 0, priv->base + WTCSR);
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return 0;
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}
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static int rza_wdt_ping(struct watchdog_device *wdev)
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{
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struct rza_wdt *priv = watchdog_get_drvdata(wdev);
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writew(WTCNT_MAGIC | 0, priv->base + WTCNT);
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return 0;
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}
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static int rza_wdt_restart(struct watchdog_device *wdev, unsigned long action,
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void *data)
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{
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struct rza_wdt *priv = watchdog_get_drvdata(wdev);
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/* Stop timer */
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writew(WTCSR_MAGIC | 0, priv->base + WTCSR);
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/* Must dummy read WRCSR:WOVF at least once before clearing */
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readb(priv->base + WRCSR);
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writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR);
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/*
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* Start timer with fastest clock source and only 1 clock left before
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* overflow with reset option enabled.
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*/
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writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR);
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writew(WTCNT_MAGIC | 255, priv->base + WTCNT);
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writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME, priv->base + WTCSR);
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/*
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* Actually make sure the above sequence hits hardware before sleeping.
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*/
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wmb();
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/* Wait for WDT overflow (reset) */
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udelay(20);
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return 0;
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}
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static const struct watchdog_info rza_wdt_ident = {
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.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
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.identity = "Renesas RZ/A WDT Watchdog",
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};
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static const struct watchdog_ops rza_wdt_ops = {
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.owner = THIS_MODULE,
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.start = rza_wdt_start,
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.stop = rza_wdt_stop,
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.ping = rza_wdt_ping,
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.restart = rza_wdt_restart,
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};
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static int rza_wdt_probe(struct platform_device *pdev)
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{
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struct rza_wdt *priv;
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struct resource *res;
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unsigned long rate;
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int ret;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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priv->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(priv->clk))
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return PTR_ERR(priv->clk);
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rate = clk_get_rate(priv->clk);
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if (rate < 16384) {
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dev_err(&pdev->dev, "invalid clock rate (%ld)\n", rate);
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return -ENOENT;
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}
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/* Assume slowest clock rate possible (CKS=7) */
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rate /= 16384;
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priv->wdev.info = &rza_wdt_ident,
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priv->wdev.ops = &rza_wdt_ops,
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priv->wdev.parent = &pdev->dev;
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/*
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* Since the max possible timeout of our 8-bit count register is less
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* than a second, we must use max_hw_heartbeat_ms.
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*/
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priv->wdev.max_hw_heartbeat_ms = (1000 * U8_MAX) / rate;
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dev_dbg(&pdev->dev, "max hw timeout of %dms\n",
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priv->wdev.max_hw_heartbeat_ms);
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priv->wdev.min_timeout = 1;
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priv->wdev.timeout = DEFAULT_TIMEOUT;
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watchdog_init_timeout(&priv->wdev, 0, &pdev->dev);
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watchdog_set_drvdata(&priv->wdev, priv);
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ret = devm_watchdog_register_device(&pdev->dev, &priv->wdev);
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if (ret)
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dev_err(&pdev->dev, "Cannot register watchdog device\n");
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return ret;
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}
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static const struct of_device_id rza_wdt_of_match[] = {
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{ .compatible = "renesas,rza-wdt", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, rza_wdt_of_match);
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static struct platform_driver rza_wdt_driver = {
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.probe = rza_wdt_probe,
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.driver = {
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.name = "rza_wdt",
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.of_match_table = rza_wdt_of_match,
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},
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};
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module_platform_driver(rza_wdt_driver);
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MODULE_DESCRIPTION("Renesas RZ/A WDT Driver");
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MODULE_AUTHOR("Chris Brandt <chris.brandt@renesas.com>");
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MODULE_LICENSE("GPL v2");
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