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[netdrvr] skfp: remove a bunch of dead code 

The driver has not compiled in anything except PCI support for many
years (see drivers/net/skfp/Makefile).  This driver is also unmaintained
for many years, so arguments for keeping the cross-OS, cross-bus (ISA,
EISA, MCA) code do not exist.

Signed-off-by: Jeff Garzik <jeff@garzik.org>
hifive-unleashed-5.1
Jeff Garzik 2007-07-24 01:30:36 -04:00 committed by David S. Miller
parent 7856a541ad
commit af096046f6
6 changed files with 8 additions and 1573 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

693
drivers/net/skfp/drvfbi.c
View File

@ -43,25 +43,6 @@ static const char ID_sccs[] = "@(#)drvfbi.c 1.63 99/02/11 (C) SK " ;
/*
* valid configuration values are:
*/
#ifdef ISA
const int opt_ints[] = {8, 3, 4, 5, 9, 10, 11, 12, 15} ;
const int opt_iops[] = {8,
0x100, 0x120, 0x180, 0x1a0, 0x220, 0x240, 0x320, 0x340};
const int opt_dmas[] = {4, 3, 5, 6, 7} ;
const int opt_eproms[] = {15, 0xc0, 0xc2, 0xc4, 0xc6, 0xc8, 0xca, 0xcc, 0xce,
0xd0, 0xd2, 0xd4, 0xd6, 0xd8, 0xda, 0xdc} ;
#endif
#ifdef EISA
const int opt_ints[] = {5, 9, 10, 11} ;
const int opt_dmas[] = {0, 5, 6, 7} ;
const int opt_eproms[] = {0xc0, 0xc2, 0xc4, 0xc6, 0xc8, 0xca, 0xcc, 0xce,
0xd0, 0xd2, 0xd4, 0xd6, 0xd8, 0xda, 0xdc} ;
#endif
#ifdef MCA
int opt_ints[] = {3, 11, 10, 9} ; /* FM1 */
int opt_eproms[] = {0, 0xc4, 0xc8, 0xcc, 0xd0, 0xd4, 0xd8, 0xdc} ;
#endif /* MCA */
/*
* xPOS_ID:xxxx
@ -78,17 +59,9 @@ int opt_eproms[] = {0, 0xc4, 0xc8, 0xcc, 0xd0, 0xd4, 0xd8, 0xdc} ;
*/
#ifndef MULT_OEM
#ifndef OEM_CONCEPT
#ifndef MCA
const u_char oem_id[] = "xPOS_ID:xxxx" ;
#else
const u_char oem_id[] = "xPOSID1:xxxx" ; /* FM1 card id. */
#endif
#else /* OEM_CONCEPT */
#ifndef MCA
const u_char oem_id[] = OEM_ID ;
#else
const u_char oem_id[] = OEM_ID1 ; /* FM1 card id. */
#endif /* MCA */
#endif /* OEM_CONCEPT */
#define ID_BYTE0 8
#define OEMID(smc,i) oem_id[ID_BYTE0 + i]
@ -109,23 +82,6 @@ extern int AIX_vpdReadByte() ;
/* Prototype of a local function. */
static void smt_stop_watchdog(struct s_smc *smc);
#ifdef MCA
static int read_card_id() ;
static void DisableSlotAccess() ;
static void EnableSlotAccess() ;
#ifdef AIX
extern int attach_POS_addr() ;
extern int detach_POS_addr() ;
extern u_char read_POS() ;
extern void write_POS() ;
extern int AIX_vpdReadByte() ;
#else
#define read_POS(smc,a1,a2) ((u_char) inp(a1))
#define write_POS(smc,a1,a2,a3) outp((a1),(a3))
#endif
#endif /* MCA */
/*
* FDDI card reset
*/
@ -139,51 +95,6 @@ static void card_start(struct s_smc *smc)
smt_stop_watchdog(smc) ;
#ifdef ISA
outpw(CSR_A,0) ; /* reset for all chips */
for (i = 10 ; i ; i--) /* delay for PLC's */
(void)inpw(ISR_A) ;
OUT_82c54_TIMER(3,COUNT(2) | RW_OP(3) | TMODE(2)) ;
/* counter 2, mode 2 */
OUT_82c54_TIMER(2,97) ; /* LSB */
OUT_82c54_TIMER(2,0) ; /* MSB ( 15.6 us ) */
outpw(CSR_A,CS_CRESET) ;
#endif
#ifdef EISA
outpw(CSR_A,0) ; /* reset for all chips */
for (i = 10 ; i ; i--) /* delay for PLC's */
(void)inpw(ISR_A) ;
outpw(CSR_A,CS_CRESET) ;
smc->hw.led = (2<<6) ;
outpw(CSR_A,CS_CRESET | smc->hw.led) ;
#endif
#ifdef MCA
outp(ADDR(CARD_DIS),0) ; /* reset for all chips */
for (i = 10 ; i ; i--) /* delay for PLC's */
(void)inpw(ISR_A) ;
outp(ADDR(CARD_EN),0) ;
/* first I/O after reset must not be a access to FORMAC or PLC */
/*
* bus timeout (MCA)
*/
OUT_82c54_TIMER(3,COUNT(2) | RW_OP(3) | TMODE(3)) ;
/* counter 2, mode 3 */
OUT_82c54_TIMER(2,(2*24)) ; /* 3.9 us * 2 square wave */
OUT_82c54_TIMER(2,0) ; /* MSB */
/* POS 102 indicated an activ Check Line or Buss Error monitoring */
if (inpw(CSA_A) & (POS_EN_CHKINT | POS_EN_BUS_ERR)) {
outp(ADDR(IRQ_CHCK_EN),0) ;
}
if (!((i = inpw(CSR_A)) & CS_SAS)) {
if (!(i & CS_BYSTAT)) {
outp(ADDR(BYPASS(STAT_INS)),0) ;/* insert station */
}
}
outpw(LEDR_A,LED_1) ; /* yellow */
#endif /* MCA */
#ifdef PCI
/*
* make sure no transfer activity is pending
@ -253,15 +164,7 @@ void card_stop(struct s_smc *smc)
{
smt_stop_watchdog(smc) ;
smc->hw.mac_ring_is_up = 0 ; /* ring down */
#ifdef ISA
outpw(CSR_A,0) ; /* reset for all chips */
#endif
#ifdef EISA
outpw(CSR_A,0) ; /* reset for all chips */
#endif
#ifdef MCA
outp(ADDR(CARD_DIS),0) ; /* reset for all chips */
#endif
#ifdef PCI
/*
* make sure no transfer activity is pending
@ -284,60 +187,6 @@ void mac1_irq(struct s_smc *smc, u_short stu, u_short stl)
{
int restart_tx = 0 ;
again:
#ifndef PCI
#ifndef ISA
/*
* FORMAC+ bug modified the queue pointer if many read/write accesses happens!?
*/
if (stl & (FM_SPCEPDS | /* parit/coding err. syn.q.*/
FM_SPCEPDA0 | /* parit/coding err. a.q.0 */
FM_SPCEPDA1 | /* parit/coding err. a.q.1 */
FM_SPCEPDA2)) { /* parit/coding err. a.q.2 */
SMT_PANIC(smc,SMT_E0132, SMT_E0132_MSG) ;
}
if (stl & (FM_STBURS | /* tx buffer underrun syn.q.*/
FM_STBURA0 | /* tx buffer underrun a.q.0 */
FM_STBURA1 | /* tx buffer underrun a.q.1 */
FM_STBURA2)) { /* tx buffer underrun a.q.2 */
SMT_PANIC(smc,SMT_E0133, SMT_E0133_MSG) ;
}
#endif
if ( (stu & (FM_SXMTABT | /* transmit abort */
#ifdef SYNC
FM_STXABRS | /* syn. tx abort */
#endif /* SYNC */
FM_STXABRA0)) || /* asyn. tx abort */
(stl & (FM_SQLCKS | /* lock for syn. q. */
FM_SQLCKA0)) ) { /* lock for asyn. q. */
formac_tx_restart(smc) ; /* init tx */
restart_tx = 1 ;
stu = inpw(FM_A(FM_ST1U)) ;
stl = inpw(FM_A(FM_ST1L)) ;
stu &= ~ (FM_STECFRMA0 | FM_STEFRMA0 | FM_STEFRMS) ;
if (stu || stl)
goto again ;
}
#ifndef SYNC
if (stu & (FM_STECFRMA0 | /* end of chain asyn tx */
FM_STEFRMA0)) { /* end of frame asyn tx */
/* free tx_queue */
smc->hw.n_a_send = 0 ;
if (++smc->hw.fp.tx_free < smc->hw.fp.tx_max) {
start_next_send(smc);
}
restart_tx = 1 ;
}
#else /* SYNC */
if (stu & (FM_STEFRMA0 | /* end of asyn tx */
FM_STEFRMS)) { /* end of sync tx */
restart_tx = 1 ;
}
#endif /* SYNC */
if (restart_tx)
llc_restart_tx(smc) ;
}
#else /* PCI */
/*
* parity error: note encoding error is not possible in tag mode
@ -378,7 +227,7 @@ again:
if (restart_tx)
llc_restart_tx(smc) ;
}
#endif /* PCI */
/*
* interrupt source= plc1
* this function is called in nwfbisr.asm
@ -387,10 +236,6 @@ void plc1_irq(struct s_smc *smc)
{
u_short st = inpw(PLC(PB,PL_INTR_EVENT)) ;
#if (defined(ISA) || defined(EISA))
/* reset PLC Int. bits */
outpw(PLC1_I,inpw(PLC1_I)) ;
#endif
plc_irq(smc,PB,st) ;
}
@ -402,10 +247,6 @@ void plc2_irq(struct s_smc *smc)
{
u_short st = inpw(PLC(PA,PL_INTR_EVENT)) ;
#if (defined(ISA) || defined(EISA))
/* reset PLC Int. bits */
outpw(PLC2_I,inpw(PLC2_I)) ;
#endif
plc_irq(smc,PA,st) ;
}
@ -446,43 +287,15 @@ void read_address(struct s_smc *smc, u_char *mac_addr)
char PmdType ;
int i ;
#if (defined(ISA) || defined(MCA))
for (i = 0; i < 4 ;i++) { /* read mac address from board */
smc->hw.fddi_phys_addr.a[i] =
bitrev8(inpw(PR_A(i+SA_MAC)));
}
for (i = 4; i < 6; i++) {
smc->hw.fddi_phys_addr.a[i] =
bitrev8(inpw(PR_A(i+SA_MAC+PRA_OFF)));
}
#endif
#ifdef EISA
/*
* Note: We get trouble on an Alpha machine if we make a inpw()
* instead of inp()
*/
for (i = 0; i < 4 ;i++) { /* read mac address from board */
smc->hw.fddi_phys_addr.a[i] =
bitrev8(inp(PR_A(i+SA_MAC)));
}
for (i = 4; i < 6; i++) {
smc->hw.fddi_phys_addr.a[i] =
bitrev8(inp(PR_A(i+SA_MAC+PRA_OFF)));
}
#endif
#ifdef PCI
for (i = 0; i < 6; i++) { /* read mac address from board */
smc->hw.fddi_phys_addr.a[i] =
bitrev8(inp(ADDR(B2_MAC_0+i)));
}
#endif
#ifndef PCI
ConnectorType = inpw(PR_A(SA_PMD_TYPE)) & 0xff ;
PmdType = inpw(PR_A(SA_PMD_TYPE+1)) & 0xff ;
#else
ConnectorType = inp(ADDR(B2_CONN_TYP)) ;
PmdType = inp(ADDR(B2_PMD_TYP)) ;
#endif
smc->y[PA].pmd_type[PMD_SK_CONN] =
smc->y[PB].pmd_type[PMD_SK_CONN] = ConnectorType ;
@ -512,20 +325,12 @@ void init_board(struct s_smc *smc, u_char *mac_addr)
card_start(smc) ;
read_address(smc,mac_addr) ;
#ifndef PCI
if (inpw(CSR_A) & CS_SAS)
#else
if (!(inp(ADDR(B0_DAS)) & DAS_AVAIL))
#endif
smc->s.sas = SMT_SAS ; /* Single att. station */
else
smc->s.sas = SMT_DAS ; /* Dual att. station */
#ifndef PCI
if (inpw(CSR_A) & CS_BYSTAT)
#else
if (!(inp(ADDR(B0_DAS)) & DAS_BYP_ST))
#endif
smc->mib.fddiSMTBypassPresent = 0 ;
/* without opt. bypass */
else
@ -538,42 +343,12 @@ void init_board(struct s_smc *smc, u_char *mac_addr)
*/
void sm_pm_bypass_req(struct s_smc *smc, int mode)
{
#if (defined(ISA) || defined(EISA))
int csra_v ;
#endif
DB_ECMN(1,"ECM : sm_pm_bypass_req(%s)\n",(mode == BP_INSERT) ?
"BP_INSERT" : "BP_DEINSERT",0) ;
if (smc->s.sas != SMT_DAS)
return ;
#if (defined(ISA) || defined(EISA))
csra_v = inpw(CSR_A) & ~CS_BYPASS ;
#ifdef EISA
csra_v |= smc->hw.led ;
#endif
switch(mode) {
case BP_INSERT :
outpw(CSR_A,csra_v | CS_BYPASS) ;
break ;
case BP_DEINSERT :
outpw(CSR_A,csra_v) ;
break ;
}
#endif /* ISA / EISA */
#ifdef MCA
switch(mode) {
case BP_INSERT :
outp(ADDR(BYPASS(STAT_INS)),0) ;/* insert station */
break ;
case BP_DEINSERT :
outp(ADDR(BYPASS(STAT_BYP)),0) ; /* bypass station */
break ;
}
#endif
#ifdef PCI
switch(mode) {
case BP_INSERT :
@ -591,31 +366,14 @@ void sm_pm_bypass_req(struct s_smc *smc, int mode)
*/
int sm_pm_bypass_present(struct s_smc *smc)
{
#ifndef PCI
return( (inpw(CSR_A) & CS_BYSTAT) ? FALSE : TRUE ) ;
#else
return( (inp(ADDR(B0_DAS)) & DAS_BYP_ST) ? TRUE: FALSE) ;
#endif
}
void plc_clear_irq(struct s_smc *smc, int p)
{
SK_UNUSED(p) ;
#if (defined(ISA) || defined(EISA))
switch (p) {
case PA :
/* reset PLC Int. bits */
outpw(PLC2_I,inpw(PLC2_I)) ;
break ;
case PB :
/* reset PLC Int. bits */
outpw(PLC1_I,inpw(PLC1_I)) ;
break ;
}
#else
SK_UNUSED(smc) ;
#endif
}
@ -645,51 +403,6 @@ static void led_indication(struct s_smc *smc, int led_event)
phy = &smc->y[PB] ;
mib_b = phy->mib ;
#ifdef EISA
/* Ring up = yellow led OFF*/
if (led_event == LED_Y_ON) {
smc->hw.led |= CS_LED_1 ;
}
else if (led_event == LED_Y_OFF) {
smc->hw.led &= ~CS_LED_1 ;
}
else {
/* Link at Port A or B = green led ON */
if (mib_a->fddiPORTPCMState == PC8_ACTIVE ||
mib_b->fddiPORTPCMState == PC8_ACTIVE) {
smc->hw.led |= CS_LED_0 ;
}
else {
smc->hw.led &= ~CS_LED_0 ;
}
}
#endif
#ifdef MCA
led_state = inpw(LEDR_A) ;
/* Ring up = yellow led OFF*/
if (led_event == LED_Y_ON) {
led_state |= LED_1 ;
}
else if (led_event == LED_Y_OFF) {
led_state &= ~LED_1 ;
}
else {
led_state &= ~(LED_2|LED_0) ;
/* Link at Port A = green led A ON */
if (mib_a->fddiPORTPCMState == PC8_ACTIVE) {
led_state |= LED_2 ;
}
/* Link at Port B/S = green led B ON */
if (mib_b->fddiPORTPCMState == PC8_ACTIVE) {
led_state |= LED_0 ;
}
}
outpw(LEDR_A, led_state) ;
#endif /* MCA */
#ifdef PCI
led_state = 0 ;
@ -824,406 +537,6 @@ int set_oi_id_def(struct s_smc *smc)
}
#endif /* MULT_OEM */
#ifdef MCA
/************************
*
* BEGIN_MANUAL_ENTRY()
*
* exist_board
*
* Check if an MCA board is present in the specified slot.
*
* int exist_board(
* struct s_smc *smc,
* int slot) ;
* In
* smc - A pointer to the SMT Context struct.
*
* slot - The number of the slot to inspect.
* Out
* 0 = No adapter present.
* 1 = Found FM1 adapter.
*
* Pseudo
* Read MCA ID
* for all valid OEM_IDs
* compare with ID read
* if equal, return 1
* return(0
*
* Note
* The smc pointer must be valid now.
*
* END_MANUAL_ENTRY()
*
************************/
#define LONG_CARD_ID(lo, hi) ((((hi) & 0xff) << 8) | ((lo) & 0xff))
int exist_board(struct s_smc *smc, int slot)
{
#ifdef MULT_OEM
SK_LOC_DECL(u_char,id[2]) ;
int idi ;
#endif /* MULT_OEM */
/* No longer valid. */
if (smc == NULL)
return(0) ;
#ifndef MULT_OEM
if (read_card_id(smc, slot)
== LONG_CARD_ID(OEMID(smc,0), OEMID(smc,1)))
return (1) ; /* Found FM adapter. */
#else /* MULT_OEM */
idi = read_card_id(smc, slot) ;
id[0] = idi & 0xff ;
id[1] = idi >> 8 ;
smc->hw.oem_id = (struct s_oem_ids *) &oem_ids[0] ;
for (; smc->hw.oem_id->oi_status != OI_STAT_LAST; smc->hw.oem_id++) {
if (smc->hw.oem_id->oi_status < smc->hw.oem_min_status)
continue ;
if (is_equal_num(&id[0],&OEMID(smc,0),2))
return (1) ;
}
#endif /* MULT_OEM */
return (0) ; /* No adapter found. */
}
/************************
*
* read_card_id
*
* Read the MCA card id from the specified slot.
* In
* smc - A pointer to the SMT Context struct.
* CAVEAT: This pointer may be NULL and *must not* be used within this
* function. It's only purpose is for drivers that need some information
* for the inp() and outp() macros.
*
* slot - The number of the slot for which the card id is returned.
* Out
* Returns the card id read from the specified slot. If an illegal slot
* number is specified, the function returns zero.
*
************************/
static int read_card_id(struct s_smc *smc, int slot)
/* struct s_smc *smc ; Do not use. */
{
int card_id ;
SK_UNUSED(smc) ; /* Make LINT happy. */
if ((slot < 1) || (slot > 15)) /* max 16 slots, 0 = motherboard */
return (0) ; /* Illegal slot number specified. */
EnableSlotAccess(smc, slot) ;
card_id = ((read_POS(smc,POS_ID_HIGH,slot - 1) & 0xff) << 8) |
(read_POS(smc,POS_ID_LOW,slot - 1) & 0xff) ;
DisableSlotAccess(smc) ;
return (card_id) ;
}
/************************
*
* BEGIN_MANUAL_ENTRY()
*
* get_board_para
*
* Get adapter configuration information. Fill all board specific
* parameters within the 'smc' structure.
*
* int get_board_para(
* struct s_smc *smc,
* int slot) ;
* In
* smc - A pointer to the SMT Context struct, to which this function will
* write some adapter configuration data.
*
* slot - The number of the slot, in which the adapter is installed.
* Out
* 0 = No adapter present.
* 1 = Ok.
* 2 = Adapter present, but card enable bit not set.
*
* END_MANUAL_ENTRY()
*
************************/
int get_board_para(struct s_smc *smc, int slot)
{
int val ;
int i ;
/* Check if adapter present & get type of adapter. */
switch (exist_board(smc, slot)) {
case 0: /* Adapter not present. */
return (0) ;
case 1: /* FM Rev. 1 */
smc->hw.rev = FM1_REV ;
smc->hw.VFullRead = 0x0a ;
smc->hw.VFullWrite = 0x05 ;
smc->hw.DmaWriteExtraBytes = 8 ; /* 2 extra words. */
break ;
}
smc->hw.slot = slot ;
EnableSlotAccess(smc, slot) ;
if (!(read_POS(smc,POS_102, slot - 1) & POS_CARD_EN)) {
DisableSlotAccess(smc) ;
return (2) ; /* Card enable bit not set. */
}
val = read_POS(smc,POS_104, slot - 1) ; /* I/O, IRQ */
#ifndef MEM_MAPPED_IO /* is defined by the operating system */
i = val & POS_IOSEL ; /* I/O base addr. (0x0200 .. 0xfe00) */
smc->hw.iop = (i + 1) * 0x0400 - 0x200 ;
#endif
i = ((val & POS_IRQSEL) >> 6) & 0x03 ; /* IRQ <0, 1> */
smc->hw.irq = opt_ints[i] ;
/* FPROM base addr. */
i = ((read_POS(smc,POS_103, slot - 1) & POS_MSEL) >> 4) & 0x07 ;
smc->hw.eprom = opt_eproms[i] ;
DisableSlotAccess(smc) ;
/* before this, the smc->hw.iop must be set !!! */
smc->hw.slot_32 = inpw(CSF_A) & SLOT_32 ;
return (1) ;
}
/* Enable access to specified MCA slot. */
static void EnableSlotAccess(struct s_smc *smc, int slot)
{
SK_UNUSED(slot) ;
#ifndef AIX
SK_UNUSED(smc) ;
/* System mode. */
outp(POS_SYS_SETUP, POS_SYSTEM) ;
/* Select slot. */
outp(POS_CHANNEL_POS, POS_CHANNEL_BIT | (slot-1)) ;
#else
attach_POS_addr (smc) ;
#endif
}
/* Disable access to MCA slot formerly enabled via EnableSlotAccess(). */
static void DisableSlotAccess(struct s_smc *smc)
{
#ifndef AIX
SK_UNUSED(smc) ;
outp(POS_CHANNEL_POS, 0) ;
#else
detach_POS_addr (smc) ;
#endif
}
#endif /* MCA */
#ifdef EISA
#ifndef MEM_MAPPED_IO
#define SADDR(slot) (((slot)<<12)&0xf000)
#else /* MEM_MAPPED_IO */
#define SADDR(slot) (smc->hw.iop)
#endif /* MEM_MAPPED_IO */
/************************
*
* BEGIN_MANUAL_ENTRY()
*
* exist_board
*
* Check if an EISA board is present in the specified slot.
*
* int exist_board(
* struct s_smc *smc,
* int slot) ;
* In
* smc - A pointer to the SMT Context struct.
*
* slot - The number of the slot to inspect.
* Out
* 0 = No adapter present.
* 1 = Found adapter.
*
* Pseudo
* Read EISA ID
* for all valid OEM_IDs
* compare with ID read
* if equal, return 1
* return(0
*
* Note
* The smc pointer must be valid now.
*
************************/
int exist_board(struct s_smc *smc, int slot)
{
int i ;
#ifdef MULT_OEM
SK_LOC_DECL(u_char,id[4]) ;
#endif /* MULT_OEM */
/* No longer valid. */
if (smc == NULL)
return(0);
SK_UNUSED(slot) ;
#ifndef MULT_OEM
for (i = 0 ; i < 4 ; i++) {
if (inp(SADDR(slot)+PRA(i)) != OEMID(smc,i))
return(0) ;
}
return(1) ;
#else /* MULT_OEM */
for (i = 0 ; i < 4 ; i++)
id[i] = inp(SADDR(slot)+PRA(i)) ;
smc->hw.oem_id = (struct s_oem_ids *) &oem_ids[0] ;
for (; smc->hw.oem_id->oi_status != OI_STAT_LAST; smc->hw.oem_id++) {
if (smc->hw.oem_id->oi_status < smc->hw.oem_min_status)
continue ;
if (is_equal_num(&id[0],&OEMID(smc,0),4))
return (1) ;
}
return (0) ; /* No adapter found. */
#endif /* MULT_OEM */
}
int get_board_para(struct s_smc *smc, int slot)
{
int i ;
if (!exist_board(smc,slot))
return(0) ;
smc->hw.slot = slot ;
#ifndef MEM_MAPPED_IO /* if defined by the operating system */
smc->hw.iop = SADDR(slot) ;
#endif
if (!(inp(C0_A(0))&CFG_CARD_EN)) {
return(2) ; /* CFG_CARD_EN bit not set! */
}
smc->hw.irq = opt_ints[(inp(C1_A(0)) & CFG_IRQ_SEL)] ;
smc->hw.dma = opt_dmas[((inp(C1_A(0)) & CFG_DRQ_SEL)>>3)] ;
if ((i = inp(C2_A(0)) & CFG_EPROM_SEL) != 0x0f)
smc->hw.eprom = opt_eproms[i] ;
else
smc->hw.eprom = 0 ;
smc->hw.DmaWriteExtraBytes = 8 ;
return(1) ;
}
#endif /* EISA */
#ifdef ISA
#ifndef MULT_OEM
const u_char sklogo[6] = SKLOGO_STR ;
#define SIZE_SKLOGO(smc) sizeof(sklogo)
#define SKLOGO(smc,i) sklogo[i]
#else /* MULT_OEM */
#define SIZE_SKLOGO(smc) smc->hw.oem_id->oi_logo_len
#define SKLOGO(smc,i) smc->hw.oem_id->oi_logo[i]
#endif /* MULT_OEM */
int exist_board(struct s_smc *smc, HW_PTR port)
{
int i ;
#ifdef MULT_OEM
int bytes_read ;
u_char board_logo[15] ;
SK_LOC_DECL(u_char,id[4]) ;
#endif /* MULT_OEM */
/* No longer valid. */
if (smc == NULL)
return(0);
SK_UNUSED(smc) ;
#ifndef MULT_OEM
for (i = SADDRL ; i < (signed) (SADDRL+SIZE_SKLOGO(smc)) ; i++) {
if ((u_char)inpw((PRA(i)+port)) != SKLOGO(smc,i-SADDRL)) {
return(0) ;
}
}
/* check MAC address (S&K or other) */
for (i = 0 ; i < 3 ; i++) {
if ((u_char)inpw((PRA(i)+port)) != OEMID(smc,i))
return(0) ;
}
return(1) ;
#else /* MULT_OEM */
smc->hw.oem_id = (struct s_oem_ids *) &oem_ids[0] ;
board_logo[0] = (u_char)inpw((PRA(SADDRL)+port)) ;
bytes_read = 1 ;
for (; smc->hw.oem_id->oi_status != OI_STAT_LAST; smc->hw.oem_id++) {
if (smc->hw.oem_id->oi_status < smc->hw.oem_min_status)
continue ;
/* Test all read bytes with current OEM_entry */
/* for (i=0; (i<bytes_read) && (i < SIZE_SKLOGO(smc)); i++) { */
for (i = 0; i < bytes_read; i++) {
if (board_logo[i] != SKLOGO(smc,i))
break ;
}
/* If mismatch, switch to next OEM entry */
if ((board_logo[i] != SKLOGO(smc,i)) && (i < bytes_read))
continue ;
--i ;
while (bytes_read < SIZE_SKLOGO(smc)) {
// inpw next byte SK_Logo
i++ ;
board_logo[i] = (u_char)inpw((PRA(SADDRL+i)+port)) ;
bytes_read++ ;
if (board_logo[i] != SKLOGO(smc,i))
break ;
}
for (i = 0 ; i < 3 ; i++)
id[i] = (u_char)inpw((PRA(i)+port)) ;
if ((board_logo[i] == SKLOGO(smc,i))
&& (bytes_read == SIZE_SKLOGO(smc))) {
if (is_equal_num(&id[0],&OEMID(smc,0),3))
return(1);
}
} /* for */
return(0) ;
#endif /* MULT_OEM */
}
int get_board_para(struct s_smc *smc, int slot)
{
SK_UNUSED(smc) ;
SK_UNUSED(slot) ;
return(0) ; /* for ISA not supported */
}
#endif /* ISA */
#ifdef PCI
#ifdef USE_BIOS_FUN
int exist_board(struct s_smc *smc, int slot)

4
drivers/net/skfp/h/mbuf.h
View File

@ -15,11 +15,7 @@
#ifndef _MBUF_
#define _MBUF_
#ifndef PCI
#define M_SIZE 4550
#else
#define M_SIZE 4504
#endif
#ifndef MAX_MBUF
#define MAX_MBUF 4

783
drivers/net/skfp/h/skfbi.h
View File

@ -21,791 +21,10 @@
#endif
/*
* physical address offset + IO-Port base address
*/
#ifndef PCI
#define ADDR(a) ((a)+smc->hw.iop)
#define ADDRS(smc,a) ((a)+(smc)->hw.iop)
#endif
/*
* FDDI-Fx (x := {I(SA), E(ISA), M(CA), P(CI)})
* FDDI-Fx (x := {I(SA), P(CI)})
* address calculation & function defines
*/
#ifdef EISA
/*
* Configuration PROM: !! all 8-Bit IO's !!
* |<- MAC-Address ->|
* /-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-/
* val: |PROD_ID0..3| | free | |00|00|5A|40| |nn|mm|00|00|
* /-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-/
* IO- ^ ^ ^ ^ ^
* port 0C80 0C83 0C88 0C90 0C98
* | \
* | \
* | \______________________________________________
* EISA Expansion Board Product ID: \
* BIT: |7 6 5 4 3 2 1 0| \
* | PROD_ID0 | PROD_ID1 | PROD_ID2 | PROD_ID3 |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |0| MAN_C0 | MAN_C1 | MAN_C2 | PROD1 | PROD0 | REV1 | REV0 |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* ^=reserved | product numb. | revision numb |
* MAN_Cx = compressed manufacterer code (x:=0..2)
* ASCII : 'A'..'Z' : 0x41..0x5A -> compr.(c-0x40) : 0x01..0x1A (5Bits!)
*/
#ifndef MULT_OEM
#ifndef OEM_CONCEPT
#define MAN_C0 ('S'-0x40)
#define MAN_C1 ('K'-0x40)
#define MAN_C2 ('D'-0x40)
#define PROD_ID0 (u_char)((MAN_C0<<2) | (MAN_C1>>3))
#define PROD_ID1 (u_char)(((MAN_C1<<5) & 0xff) | MAN_C2)
#define PROD_ID2 (u_char)(1) /* prod. nr. */
#define PROD_ID3 (u_char)(0) /* rev. nr. */
#ifndef OEM_USER_DATA
#define OEM_USER_DATA "SK-NET FDDI V2.0 Userdata"
#endif
#else /* OEM_CONCEPT */
/* MAN_C(0|1|2) no longer present (ra). */
#define PROD_ID0 (u_char)OEM_PROD_ID0
#define PROD_ID1 (u_char)OEM_PROD_ID1
#define PROD_ID2 (u_char)OEM_PROD_ID2
#define PROD_ID3 (u_char)OEM_PROD_ID3
#endif /* OEM_CONCEPT */
#define SKLOGO PROD_ID0, PROD_ID1, PROD_ID2, PROD_ID3
#endif /* MULT_OEM */
#define SADDRL (0) /* start address SKLOGO */
#define SA_MAC (0x10) /* start addr. MAC_AD within the PROM */
#define PRA_OFF (4)
#define SA_PMD_TYPE (8) /* start addr. PMD-Type */
#define SKFDDI_PSZ 32 /* address PROM size */
/*
* address transmission from logical to physical offset address on board
*/
#define FMA(a) (0x0400|((a)<<1)) /* FORMAC+ (r/w) */
#define P1A(a) (0x0800|((a)<<1)) /* PLC1 (r/w) */
#define P2A(a) (0x0840|((a)<<1)) /* PLC2 (r/w) */
#define TIA(a) (0x0880|((a)<<1)) /* Timer (r/w) */
#define PRA(a) (0x0c80| (a)) /* configuration PROM */
#define C0A(a) (0x0c84| (a)) /* config. RAM */
#define C1A(a) (0x0ca0| (a)) /* IRQ-, DMA-nr., EPROM type */
#define C2A(a) (0x0ca4| (a)) /* EPROM and PAGE selector */
#define CONF C0A(0) /* config RAM (card enable bit port) */
#define PGRA C2A(0) /* Flash page register */
#define CDID PRA(0) /* Card ID I/O port addr. offset */
/*
* physical address offset + slot specific IO-Port base address
*/
#define FM_A(a) (FMA(a)+smc->hw.iop) /* FORMAC Plus physical addr */
#define P1_A(a) (P1A(a)+smc->hw.iop) /* PLC1 (r/w) */
#define P2_A(a) (P2A(a)+smc->hw.iop) /* PLC2 (r/w) */
#define TI_A(a) (TIA(a)+smc->hw.iop) /* Timer (r/w) */
#define PR_A(a) (PRA(a)+smc->hw.iop) /* config. PROM */
#define C0_A(a) (C0A(a)+smc->hw.iop) /* config. RAM */
#define C1_A(a) (C1A(a)+smc->hw.iop) /* config. RAM */
#define C2_A(a) (C2A(a)+smc->hw.iop) /* config. RAM */
#define CSRA 0x0008 /* control/status register address (r/w) */
#define ISRA 0x0008 /* int. source register address (upper 8Bits) */
#define PLC1I 0x001a /* clear PLC1 interrupt (write only) */
#define PLC2I 0x0020 /* clear PLC2 interrupt (write only) */
#define CSFA 0x001c /* control/status FIFO BUSY flags (read only) */
#define RQAA 0x001c /* Request reg. (write only) */
#define WCTA 0x001e /* word counter (r/w) */
#define FFLAG 0x005e /* FLAG/V_FULL (FIFO almost full, write only)*/
#define CSR_A (CSRA+smc->hw.iop) /* control/status register address (r/w) */
#ifdef UNIX
#define CSR_AS(smc) (CSRA+(smc)->hw.iop) /* control/status register address (r/w) */
#endif
#define ISR_A (ISRA+smc->hw.iop) /* int. source register address (upper 8Bits) */
#define PLC1_I (PLC1I+smc->hw.iop) /* clear PLC1 internupt (write only) */
#define PLC2_I (PLC2I+smc->hw.iop) /* clear PLC2 interrupt (write only) */
#define CSF_A (CSFA+smc->hw.iop) /* control/status FIFO BUSY flags (r/w) */
#define RQA_A (RQAA+smc->hw.iop) /* Request reg. (write only) */
#define WCT_A (WCTA+smc->hw.iop) /* word counter (r/w) */
#define FFLAG_A (FFLAG+smc->hw.iop) /* FLAG/V_FULL (FIFO almost full, write only)*/
/*
* control/status register CSRA bits
*/
/* write */
#define CS_CRESET 0x01 /* Card reset (0=reset) */
#define CS_RESET_FIFO 0x02 /* FIFO reset (0=reset) */
#define CS_IMSK 0x04 /* enable IRQ (1=enable, 0=disable) */
#define CS_EN_IRQ_TC 0x08 /* enable IRQ from transfer counter */
#define CS_BYPASS 0x20 /* bypass switch (0=remove, 1=insert)*/
#define CS_LED_0 0x40 /* switch LED 0 */
#define CS_LED_1 0x80 /* switch LED 1 */
/* read */
#define CS_BYSTAT 0x40 /* 0=Bypass exist, 1= ..not */
#define CS_SAS 0x80 /* single attachement station (=1) */
/*
* control/status register CSFA bits (FIFO)
*/
#define CSF_MUX0 0x01
#define CSF_MUX1 0x02
#define CSF_HSREQ0 0x04
#define CSF_HSREQ1 0x08
#define CSF_HSREQ2 0x10
#define CSF_BUSY_DMA 0x40
#define CSF_BUSY_FIFO 0x80
/*
* Interrupt source register ISRA (upper 8 data bits) read only & low activ.
*/
#define IS_MINTR1 0x0100 /* FORMAC ST1U/L & ~IMSK1U/L*/
#define IS_MINTR2 0x0200 /* FORMAC ST2U/L & ~IMSK2U/L*/
#define IS_PLINT1 0x0400 /* PLC1 */
#define IS_PLINT2 0x0800 /* PLC2 */
#define IS_TIMINT 0x1000 /* Timer 82C54-2 */
#define IS_TC 0x2000 /* transf. counter */
#define ALL_IRSR (IS_MINTR1|IS_MINTR2|IS_PLINT1|IS_PLINT2|IS_TIMINT|IS_TC)
/*
* CONFIG<0> RAM (C0_A())
*/
#define CFG_CARD_EN 0x01 /* card enable */
/*
* CONFIG<1> RAM (C1_A())
*/
#define CFG_IRQ_SEL 0x03 /* IRQ select (4 nr.) */
#define CFG_IRQ_TT 0x04 /* IRQ trigger type (LEVEL/EDGE) */
#define CFG_DRQ_SEL 0x18 /* DMA requ. (4 nr.) */
#define CFG_BOOT_EN 0x20 /* 0=BOOT-, 1=Application Software */
#define CFG_PROG_EN 0x40 /* V_Prog for FLASH_PROM (1=on) */
/*
* CONFIG<2> RAM (C2_A())
*/
#define CFG_EPROM_SEL 0x0f /* FPROM start address selection */
#define CFG_PAGE 0xf0 /* FPROM page selection */
#define READ_PROM(a) ((u_char)inp(a))
#define GET_PAGE(i) outp(C2_A(0),((int)(i)<<4) | (inp(C2_A(0)) & ~CFG_PAGE))
#define FPROM_SW() (inp(C1_A(0)) & CFG_BOOT_EN)
#define MAX_PAGES 16 /* 16 pages */
#define MAX_FADDR 0x2000 /* 8K per page */
#define VPP_ON() outp(C1_A(0),inp(C1_A(0)) | CFG_PROG_EN)
#define VPP_OFF() outp(C1_A(0),inp(C1_A(0)) & ~CFG_PROG_EN)
#define DMA_BUSY() (inpw(CSF_A) & CSF_BUSY_DMA)
#define FIFO_BUSY() (inpw(CSF_A) & CSF_BUSY_FIFO)
#define DMA_FIFO_BUSY() (inpw(CSF_A) & (CSF_BUSY_DMA | CSF_BUSY_FIFO))
#define BUS_CHECK()
#ifdef UNISYS
/* For UNISYS use another macro with drv_usecewait function */
#define CHECK_DMA() {u_long k = 1000000; \
while (k && (DMA_BUSY())) { k--; drv_usecwait(20); } \
if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
#else
#define CHECK_DMA() {u_long k = 1000000 ;\
while (k && (DMA_BUSY())) k-- ;\
if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
#endif
#define CHECK_FIFO() {u_long k = 1000000 ;\
while (k && (FIFO_BUSY())) k-- ;\
if (!k) SMT_PANIC(smc,HWM_E0019,HWM_E0019_MSG) ; }
#define CHECK_DMA_FIFO() {u_long k = 1000000 ;\
while (k && (DMA_FIFO_BUSY())) k-- ;\
if (!k) SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ; }
#define GET_ISR() ~inpw(ISR_A)
#define CHECK_ISR() ~inpw(ISR_A)
#ifndef UNIX
#ifndef WINNT
#define CLI_FBI() outpw(CSR_A,(inpw(CSR_A)&\
(CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|smc->hw.led)
#else /* WINNT */
#define CLI_FBI() outpw(CSR_A,(l_inpw(CSR_A)&\
(CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|smc->hw.led)
#endif /* WINNT */
#else /* UNIX */
#define CLI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc))&\
(CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|(smc)->hw.led)
#endif
#ifndef UNIX
#define STI_FBI() outpw(CSR_A,(inpw(CSR_A)&\
(CS_CRESET|CS_BYPASS|CS_RESET_FIFO))|CS_IMSK|smc->hw.led)
#else
#define STI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc))&\
(CS_CRESET|CS_BYPASS|CS_RESET_FIFO))|CS_IMSK|(smc)->hw.led)
#endif
/* EISA DMA Controller */
#define DMA_WRITE_SINGLE_MASK_BIT_M 0x0a /* Master DMA Controller */
#define DMA_WRITE_SINGLE_MASK_BIT_S 0xd4 /* Slave DMA Controller */
#define DMA_CLEAR_BYTE_POINTER_M 0x0c
#define DMA_CLEAR_BYTE_POINTER_S 0xd8
#endif /* EISA */
#ifdef MCA
/*
* POS Register: !! all I/O's are 8-Bit !!
*/
#define POS_SYS_SETUP 0x94 /* system setup register */
#define POS_SYSTEM 0xff /* system mode */
#define POS_CHANNEL_POS 0x96 /* register slot ID */
#define POS_CHANNEL_BIT 0x08 /* mask for -"- */
#define POS_BASE 0x100 /* POS base address */
#define POS_ID_LOW POS_BASE /* card ID low */
#define POS_ID_HIGH (POS_BASE+1) /* card ID high */
#define POS_102 (POS_BASE+2) /* card en., arbitration level .. */
#define POS_103 (POS_BASE+3) /* FPROM addr, page */
#define POS_104 (POS_BASE+4) /* I/O, IRQ */
#define POS_105 (POS_BASE+5) /* POS_CHCK */
#define POS_106 (POS_BASE+6) /* to read VPD */
#define POS_107 (POS_BASE+7) /* added without function */
/* FM1 card IDs */
#define FM1_CARD_ID0 0x83
#define FM1_CARD_ID1 0
#define FM1_IBM_ID0 0x9c
#define FM1_IBM_ID1 0x8f
/* FM2 card IDs */
#define FM2_CARD_ID0 0xab
#define FM2_CARD_ID1 0
#define FM2_IBM_ID0 0x7e
#define FM2_IBM_ID1 0x8f
/* Board revision. */
#define FM1_REV 0
#define FM2_REV 1
#define MAX_SLOT 8
/*
* POS_102
*/
#define POS_CARD_EN 0x01 /* card enable =1 */
#define POS_SDAT_EN 0x02 /* enable 32-bit streaming data mode */
#define POS_EN_CHKINT 0x04 /* enable int. from check line asserted */
#define POS_EN_BUS_ERR 0x08 /* enable int. on invalid busmaster transf. */
#define POS_FAIRNESS 0x10 /* fairnes on =1 */
/* attention: arbitration level used with bit 0 POS 105 */
#define POS_LARBIT 0xe0 /* arbitration level (0,0,0)->level = 0x8
(1,1,1)->level = 0xf */
/*
* POS_103
*/
#define POS_PAGE 0x07 /* FPROM page selection */
#define POS_BOOT_EN 0x08 /* boot PROM enable =1 */
#define POS_MSEL 0x70 /* memory start address for FPROM mapping */
#define PROG_EN 0x80 /* FM1: Vpp prog on/off */
#define POS_SDR 0x80 /* FM2: Streaming data bit */
/*
* POS_104
*/
#define POS_IOSEL 0x3f /* selected I/O base address */
#define POS_IRQSEL 0xc0 /* selected interrupt */
/*
* POS_105
*/
#define POS_CHCK 0x80
#define POS_SYNC_ERR 0x20 /* FM2: synchronous error reporting */
#define POS_PAR_DATA 0x10 /* FM2: data parity enable bit */
#define POS_PAR_ADDR 0x08 /* FM2: address parity enable bit */
#define POS_IRQHSEL 0x02 /* FM2: Highest bit for IRQ_selection */
#define POS_HARBIT 0x01 /* Highest bit in Bus arbitration selection */
#define SA_MAC (0) /* start addr. MAC_AD within the PROM */
#define PRA_OFF (0)
#define SA_PMD_TYPE (8) /* start addr. PMD-Type */
/*
* address transmission from logical to physical offset address on board
*/
#define FMA(a) (0x0100|((a)<<1)) /* FORMAC+ (r/w) */
#define P2(a) (0x00c0|((a)<<1)) /* PLC2 (r/w) (DAS) */
#define P1(a) (0x0080|((a)<<1)) /* PLC1 (r/w) */
#define TI(a) (0x0060|((a)<<1)) /* Timer (r/w) */
#define PR(a) (0x0040|((a)<<1)) /* configuration PROM */
#define CS(a) (0x0020| (a)) /* control/status */
#define FF(a) (0x0010|((a)<<1)) /* FIFO ASIC */
#define CT(a) (0x0000|((a)<<1)) /* counter */
/*
* counter
*/
#define ACLA CT(0) /* address counter low */
#define ACHA CT(1) /* address counter high */
#define BCN CT(2) /* byte counter */
#define MUX CT(3) /* MUX-register */
#define WCN CT(0x08) /* word counter */
#define FFLG CT(0x09) /* FIFO Flags */
/*
* test/control register (FM2 only)
*/
#define CNT_TST 0x018 /* Counter test control register */
#define CNT_STP 0x01a /* Counter test step reg. (8 Bit) */
/*
* CS register (read only)
*/
#define CSRA CS(0) /* control/status register address */
#define CSFA CS(2) /* control/status FIFO BUSY ... */
#define ISRA CS(4) /* first int. source register address */
#define ISR2 CS(6) /* second int. source register address */
#define LEDR CS(0x0c) /* LED register r/w */
#define CSIL CS(0x10) /* I/O mapped POS_ID_low (100) */
#define CSIH CS(0x12) /* - " - POS_ID_HIGH (101) */
#define CSA CS(0x14) /* - " - POS_102 */
#define CSM CS(0x0e) /* - " - POS_103 */
#define CSM_FM1 CS(0x16) /* - " - POS_103 (copy in FM1) */
#define CSI CS(0x18) /* - " - POS_104 */
#define CSS CS(0x1a) /* - " - POS_105 */
#define CSP_06 CS(0x1c) /* - " - POS_106 */
#define WDOG_ST 0x1c /* Watchdog status (FM2 only) */
#define WDOG_EN 0x1c /* Watchdog enabling (FM2 only, 8Bit) */
#define WDOG_DIS 0x1e /* Watchdog disabling (FM2 only, 8Bit) */
#define PGRA CSM /* Flash page register */
#define WCTA FF(0) /* word counter */
#define FFLAG FF(1) /* FLAG/V_FULL (FIFO almost full, write only)*/
/*
* Timer register (FM2 only)
*/
#define RTM_CNT 0x28 /* RTM Counter */
#define TI_DIV 0x60 /* Timer Prescaler */
#define TI_CH1 0x62 /* Timer channel 1 counter */
#define TI_STOP 0x64 /* Stop timer on channel 1 */
#define TI_STRT 0x66 /* Start timer on channel 1 */
#define TI_INI2 0x68 /* Timer: Bus master preemption */
#define TI_CNT2 0x6a /* Timer */
#define TI_INI3 0x6c /* Timer: Streaming data */
#define TI_CNT3 0x6e /* Timer */
#define WDOG_LO 0x70 /* Watchdog counter low */
#define WDOG_HI 0x72 /* Watchdog counter high */
#define RTM_PRE 0x74 /* restr. token prescaler */
#define RTM_TIM 0x76 /* restr. token timer */
/*
* Recommended Timeout values (for FM2 timer only)
*/
#define TOUT_BM_PRE 188 /* 3.76 usec */
#define TOUT_S_DAT 374 /* 7.48 usec */
/*
* CS register (write only)
*/
#define HSR(p) CS(0x18|(p)) /* Host request register */
#define RTM_PUT 0x36 /* restr. token counter write */
#define RTM_GET 0x28 /* - " - clear */
#define RTM_CLEAR 0x34 /* - " - read */
/*
* BCN Bit definitions
*/
#define BCN_BUSY 0x8000 /* DMA Busy flag */
#define BCN_AZERO 0x4000 /* Almost zero flag (BCN < 4) */
#define BCN_STREAM 0x2000 /* Allow streaming data (BCN >= 8) */
/*
* WCN Bit definitions
*/
#define WCN_ZERO 0x2000 /* Zero flag (counted to zero) */
#define WCN_AZERO 0x1000 /* Almost zero flag (BCN < 4) */
/*
* CNT_TST Bit definitions
*/
#define CNT_MODE 0x01 /* Go into test mode */
#define CNT_D32 0x02 /* 16/32 BIT test mode */
/*
* FIFO Flag FIFO Flags/Vfull register
*/
#define FF_VFULL 0x003f /* V_full value mask */
#define FFLG_FULL 0x2000 /* FULL flag */
#define FFLG_A_FULL 0x1000 /* Almost full flag */
#define FFLG_VFULL 0x0800 /* V_full Flag */
#define FFLG_A_EMP 0x0400 /* almost empty flag */
#define FFLG_EMP 0x0200 /* empty flag */
#define FFLG_T_EMP 0x0100 /* totally empty flag */
/*
* WDOG Watchdog status register
*/
#define WDOG_ALM 0x01 /* Watchdog alarm Bit */
#define WDOG_ACT 0x02 /* Watchdog active Bit */
/*
* CS(0) CONTROLS
*/
#define CS_CRESET 0x0001
#define FIFO_RST 0x0002
#define CS_IMSK 0x0004
#define EN_IRQ_CHCK 0x0008
#define EN_IRQ_TOKEN 0x0010
#define EN_IRQ_TC 0x0020
#define TOKEN_STATUS 0x0040
#define RTM_CHANGE 0x0080
#define CS_SAS 0x0100
#define CS_BYSTAT 0x0200 /* bypass connected (0=conn.) */
#define CS_BYPASS 0x0400 /* bypass on/off indication */
/*
* CS(2) FIFOSTAT
*/
#define HSREQ 0x0007
#define BIGDIR 0x0008
#define CSF_BUSY_FIFO 0x0010
#define CSF_BUSY_DMA 0x0020
#define SLOT_32 0x0040
#define LED_0 0x0001
#define LED_1 0x0002
#define LED_2 0x0100
#define MAX_PAGES 8 /* pages */
#define MAX_FADDR 0x4000 /* 16K per page */
/*
* IRQ = ISRA || ISR2 ;
*
* ISRA = IRQ_OTH_EN && (IS_LAN | IS_BUS) ;
* ISR2 = IRQ_TC_EN && IS_TC ;
*
* IS_LAN = (IS_MINTR1 | IS_MINTR2 | IS_PLINT1 | IS_PLINT2 | IS_TIMINT) ||
* (IRQ_EN_TOKEN && IS_TOKEN) ;
* IS_BUS = IRQ_CHCK_EN && (IS_BUSERR | IS_CHCK_L) ;
*/
/*
* ISRA !!! activ high !!!
*/
#define IS_MINTR1 0x0001 /* FORMAC ST1U/L & ~IMSK1U/L*/
#define IS_MINTR2 0x0002 /* FORMAC ST2U/L & ~IMSK2U/L*/
#define IS_PLINT1 0x0004 /* PLC1 */
#define IS_PLINT2 0x0008 /* PLC2 */
#define IS_TIMINT 0x0010 /* Timer 82C54-2 */
#define IS_TOKEN 0x0020 /* restrictet token monitoring */
#define IS_CHCK_L 0x0040 /* check line asserted */
#define IS_BUSERR 0x0080 /* bus error */
/*
* ISR2
*/
#define IS_TC 0x0001 /* terminal count irq */
#define IS_SFDBKRTN 0x0002 /* selected feedback return */
#define IS_D16 0x0004 /* DS16 */
#define IS_D32 0x0008 /* DS32 */
#define IS_DPEI 0x0010 /* Data Parity Indication */
#define ALL_IRSR 0x00ff
#define FM_A(a) ADDR(FMA(a)) /* FORMAC Plus physical addr */
#define P1_A(a) ADDR(P1(a)) /* PLC1 (r/w) */
#define P2_A(a) ADDR(P2(a)) /* PLC2 (r/w) (DAS) */
#define TI_A(a) ADDR(TI(a)) /* Timer (r/w) FM1 only! */
#define PR_A(a) ADDR(PR(a)) /* config. PROM */
#define CS_A(a) ADDR(CS(a)) /* control/status */
#define ISR1_A ADDR(ISRA) /* first int. source register address */
#define ISR2_A ADDR(ISR2) /* second -"- */
#define CSR_A ADDR(CSRA) /* control/status register address */
#define CSF_A ADDR(CSFA) /* control/status FIFO BUSY flags (r/w) */
#define CSIL_A ADDR(CSIL) /* I/O mapped POS_ID_low (102) */
#define CSIH_A ADDR(CSIH) /* - " - POS_ID_HIGH (101) */
#define CSA_A ADDR(CSA) /* - " - POS_102 */
#define CSI_A ADDR(CSI) /* - " - POS_104 */
#define CSM_A ADDR(CSM) /* - " - POS_103 */
#define CSM_FM1_A ADDR(CSM_FM1) /* - " - POS_103 (2nd copy, FM1) */
#define CSP_06_A ADDR(CSP_06) /* - " - POS_106 */
#define WCT_A ADDR(WCTA) /* word counter (r/w) */
#define FFLAG_A ADDR(FFLAG) /* FLAG/V_FULL (FIFO almost full, write only)*/
#define ACL_A ADDR(ACLA) /* address counter low */
#define ACH_A ADDR(ACHA) /* address counter high */
#define BCN_A ADDR(BCN) /* byte counter */
#define MUX_A ADDR(MUX) /* MUX-register */
#define ISR_A ADDR(ISRA) /* Interrupt Source Register */
#define FIFO_RESET_A ADDR(FIFO_RESET) /* reset the FIFO */
#define FIFO_EN_A ADDR(FIFO_EN) /* enable the FIFO */
#define WDOG_EN_A ADDR(WDOG_EN) /* reset and start the WDOG */
#define WDOG_DIS_A ADDR(WDOG_DIS) /* disable the WDOG */
/*
* all control reg. (read!) are 8 bit (except PAGE_RG_A and LEDR_A)
*/
#define HSR_A(p) ADDR(HSR(p)) /* Host request register */
#define STAT_BYP 0 /* bypass station */
#define STAT_INS 2 /* insert station */
#define BYPASS(o) CS(0x10|(o)) /* o=STAT_BYP || STAT_INS */
#define IRQ_TC_EN CS(0x0b) /* enable/disable IRQ on TC */
#define IRQ_TC_DIS CS(0x0a)
#define IRQ_TOKEN_EN CS(9) /* enable/disable IRQ on restr. Token */
#define IRQ_TOKEN_DIS CS(8)
#define IRQ_CHCK_EN CS(7) /* -"- IRQ after CHCK line */
#define IRQ_CHCK_DIS CS(6)
#define IRQ_OTH_EN CS(5) /* -"- other IRQ's */
#define IRQ_OTH_DIS CS(4)
#define FIFO_EN CS(3) /* disable (reset), enable FIFO */
#define FIFO_RESET CS(2)
#define CARD_EN CS(1) /* disable (reset), enable card */
#define CARD_DIS CS(0)
#define LEDR_A ADDR(LEDR) /* D0=green, D1=yellow, D8=L2 */
#define PAGE_RG_A ADDR(CSM) /* D<2..0> */
#define IRQ_CHCK_EN_A ADDR(IRQ_CHCK_EN)
#define IRQ_CHCK_DIS_A ADDR(IRQ_CHCK_DIS)
#define GET_PAGE(bank) outpw(PAGE_RG_A,(inpw(PAGE_RG_A) &\
(~POS_PAGE)) |(int) (bank))
#define VPP_ON() if (smc->hw.rev == FM1_REV) { \
outpw(PAGE_RG_A, \
(inpw(PAGE_RG_A) & POS_PAGE) | PROG_EN); \
}
#define VPP_OFF() if (smc->hw.rev == FM1_REV) { \
outpw(PAGE_RG_A,(inpw(PAGE_RG_A) & POS_PAGE)); \
}
#define SKFDDI_PSZ 16 /* address PROM size */
#define READ_PROM(a) ((u_char)inp(a))
#define GET_ISR() ~inpw(ISR1_A)
#ifndef TCI
#define CHECK_ISR() ~inpw(ISR1_A)
#define CHECK_ISR_SMP(iop) ~inpw((iop)+ISRA)
#else
#define CHECK_ISR() (~inpw(ISR1_A) | ~inpw(ISR2_A))
#define CHECK_ISR_SMP(iop) (~inpw((iop)+ISRA) | ~inpw((iop)+ISR2))
#endif
#define DMA_BUSY() (inpw(CSF_A) & CSF_BUSY_DMA)
#define FIFO_BUSY() (inpw(CSF_A) & CSF_BUSY_FIFO)
#define DMA_FIFO_BUSY() (inpw(CSF_A) & (CSF_BUSY_DMA | CSF_BUSY_FIFO))
#define BUS_CHECK() { int i ; \
if ((i = GET_ISR()) & IS_BUSERR) \
SMT_PANIC(smc,HWM_E0020,HWM_E0020_MSG) ; \
if (i & IS_CHCK_L) \
SMT_PANIC(smc,HWM_E0014,HWM_E0014_MSG) ; \
}
#define CHECK_DMA() { u_long k = 10000 ; \
while (k && (DMA_BUSY())) { \
k-- ; \
BUS_CHECK() ; \
} \
if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
#define CHECK_FIFO() {u_long k = 1000000 ;\
while (k && (FIFO_BUSY())) k-- ;\
if (!k) SMT_PANIC(smc,HWM_E0019,HWM_E0019_MSG) ; }
#define CHECK_DMA_FIFO() {u_long k = 1000000 ;\
while (k && (DMA_FIFO_BUSY())) { \
k-- ;\
BUS_CHECK() ; \
} \
if (!k) SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ; }
#ifndef UNIX
#define CLI_FBI() outp(ADDR(IRQ_OTH_DIS),0)
#else
#define CLI_FBI(smc) outp(ADDRS((smc),IRQ_OTH_DIS),0)
#endif
#ifndef TCI
#define CLI_FBI_SMP(iop) outp((iop)+IRQ_OTH_DIS,0)
#else
#define CLI_FBI_SMP(iop) outp((iop)+IRQ_OTH_DIS,0) ;\
outp((iop)+IRQ_TC_DIS,0)
#endif
#ifndef UNIX
#define STI_FBI() outp(ADDR(IRQ_OTH_EN),0)
#else
#define STI_FBI(smc) outp(ADDRS((smc),IRQ_OTH_EN),0)
#endif
/*
* Terminal count primitives
*/
#define CLI_TCI(smc) outp(ADDRS((smc),IRQ_TC_DIS),0)
#define STI_TCI(smc) outp(ADDRS((smc),IRQ_TC_EN),0)
#define CHECK_TC(smc,k) {(k) = 10000 ;\
while ((k) && (~inpw(ISR2_A) & IS_TC)) (k)-- ;\
if (!k) SMT_PANIC(smc,HWM_E0018,HWM_E0018_MSG) ; }
#endif /* MCA */
#ifdef ISA
/*
* address transmission from logic NPADDR6-0 to physical offset address on board
*/
#define FMA(a) (0x8000|(((a)&0x07)<<1)|(((a)&0x78)<<7)) /* FORMAC+ (r/w) */
#define PRA(a) (0x1000|(((a)&0x07)<<1)|(((a)&0x18)<<7)) /* PROM (read only)*/
#define P1A(a) (0x4000|(((a)&0x07)<<1)|(((a)&0x18)<<7)) /* PLC1 (r/w) */
#define P2A(a) (0x5000|(((a)&0x07)<<1)|(((a)&0x18)<<7)) /* PLC2 (r/w) */
#define TIA(a) (0x6000|(((a)&0x03)<<1)) /* Timer (r/w) */
#define ISRA 0x0000 /* int. source register address (read only) */
#define ACLA 0x0000 /* address counter low address (write only) */
#define ACHA 0x0002 /* address counter high address (write only) */
#define TRCA 0x0004 /* transfer counter address (write only) */
#define PGRA 0x0006 /* page register address (write only) */
#define RQAA 0x2000 /* Request reg. (write only) */
#define CSRA 0x3000 /* control/status register address (r/w) */
/*
* physical address offset + IO-Port base address
*/
#define FM_A(a) (FMA(a)+smc->hw.iop) /* FORMAC Plus physical addr */
#define PR_A(a) (PRA(a)+smc->hw.iop) /* PROM (read only)*/
#define P1_A(a) (P1A(a)+smc->hw.iop) /* PLC1 (r/w) */
#define P2_A(a) (P2A(a)+smc->hw.iop) /* PLC2 (r/w) */
#define TI_A(a) (TIA(a)+smc->hw.iop) /* Timer (r/w) */
#define ISR_A (0x0000+smc->hw.iop) /* int. source register address (read only) */
#define ACL_A (0x0000+smc->hw.iop) /* address counter low address (write only) */
#define ACH_A (0x0002+smc->hw.iop) /* address counter high address (write only)*/
#define TRC_A (0x0004+smc->hw.iop) /* transfer counter address (write only) */
#define PGR_A (0x0006+smc->hw.iop) /* page register address (write only) */
#define RQA_A (0x2000+smc->hw.iop) /* Request reg. (write only) */
#define CSR_A (0x3000+smc->hw.iop) /* control/status register address (r/w) */
#ifdef UNIX
#define CSR_AS(smc) (0x3000+(smc)->hw.iop) /* control/status register address */
#endif
#define PLC1_I (0x3400+smc->hw.iop) /* clear PLC1 interrupt bit */
#define PLC2_I (0x3800+smc->hw.iop) /* clear PLC2 interrupt bit */
#ifndef MULT_OEM
#ifndef OEM_CONCEPT
#define SKLOGO_STR "SKFDDI"
#else /* OEM_CONCEPT */
#define SKLOGO_STR OEM_FDDI_LOGO
#endif /* OEM_CONCEPT */
#endif /* MULT_OEM */
#define SADDRL (24) /* start address SKLOGO */
#define SA_MAC (0) /* start addr. MAC_AD within the PROM */
#define PRA_OFF (0)
#define SA_PMD_TYPE (8) /* start addr. PMD-Type */
#define CDID (PRA(SADDRL)) /* Card ID int/O port addr. offset */
#define NEXT_CDID ((PRA(SADDRL+1)) - CDID)
#define SKFDDI_PSZ 32 /* address PROM size */
#define READ_PROM(a) ((u_char)inpw(a))
#define GET_PAGE(i) outpw(PGR_A,(int)(i))
#define MAX_PAGES 16 /* 16 pages */
#define MAX_FADDR 0x2000 /* 8K per page */
#define VPP_OFF() outpw(CSR_A,(inpw(CSR_A) & (CS_CRESET|CS_BYPASS)))
#define VPP_ON() outpw(CSR_A,(inpw(CSR_A) & (CS_CRESET|CS_BYPASS)) | \
CS_VPPSW)
/*
* control/status register CSRA bits (log. addr: 0x3000)
*/
/* write */
#define CS_CRESET 0x01 /* Card reset (0=reset) */
#define CS_IMSK 0x02 /* enable IRQ (1=enable, 0=disable) */
#define CS_RESINT1 0x04 /* PLINT1 reset */
#define CS_VPPSW 0x10 /* 12V power switch (0=off, 1=on) */
#define CS_BYPASS 0x20 /* bypass switch (0=remove, 1=insert)*/
#define CS_RESINT2 0x40 /* PLINT2 reset */
/* read */
#define CS_BUSY 0x04 /* master transfer activ (=1) */
#define CS_SW_EPROM 0x08 /* 0=Application Soft. 1=BOOT-EPROM */
#define CS_BYSTAT 0x40 /* 0=Bypass exist, 1= ..not */
#define CS_SAS 0x80 /* single attachement station (=1) */
/*
* Interrupt source register ISRA (log. addr: 0x0000) read only & low activ.
*/
#define IS_MINTR1 0x01 /* FORMAC ST1U/L && ~IMSK1U/L*/
#define IS_MINTR2 0x02 /* FORMAC ST2U/L && ~IMSK2U/L*/
#define IS_PLINT1 0x04 /* PLC1 */
#define IS_PLINT2 0x08 /* PLC2 */
#define IS_TIMINT 0x10 /* Timer 82C54-2 */
#define ALL_IRSR (IS_MINTR1|IS_MINTR2|IS_PLINT1|IS_PLINT2|IS_TIMINT)
#define FPROM_SW() (inpw(CSR_A)&CS_SW_EPROM)
#define DMA_BUSY() (inpw(CSR_A)&CS_BUSY)
#define CHECK_FIFO()
#define BUS_CHECK()
/*
* set Host Request register (wr.)
*/
#define SET_HRQ(qup) outpw(RQA_A+((qup)<<1),0)
#ifndef UNIX
#ifndef WINNT
#define CLI_FBI() outpw(CSR_A,(inpw(CSR_A)&(CS_CRESET|CS_BYPASS|CS_VPPSW)))
#else
#define CLI_FBI() outpw(CSR_A,(l_inpw(CSR_A) & \
(CS_CRESET|CS_BYPASS|CS_VPPSW)))
#endif
#else
#define CLI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc))& \
(CS_CRESET|CS_BYPASS|CS_VPPSW)))
#endif
#ifndef UNIX
#define STI_FBI() outpw(CSR_A,(inpw(CSR_A) & \
(CS_CRESET|CS_BYPASS|CS_VPPSW)) | CS_IMSK)
#else
#define STI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc)) & \
(CS_CRESET|CS_BYPASS|CS_VPPSW)) | CS_IMSK)
#endif
#define CHECK_DMA() {unsigned k = 10000 ;\
while (k && (DMA_BUSY())) k-- ;\
if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
#define GET_ISR() ~inpw(ISR_A)
#endif /* ISA */
/*--------------------------------------------------------------------------*/
#ifdef PCI

26
drivers/net/skfp/h/skfbiinc.h
View File

@ -22,32 +22,6 @@
*/
#define ERR_FLAGS (FS_MSRABT | FS_SEAC2 | FS_SFRMERR | FS_SFRMTY1)
#ifdef ISA
#define DMA_BUSY_CHECK CSRA
#define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT)
#define HRQR (RQAA+(RQ_RRQ<<1))
#define HRQW (RQAA+(RQ_WA2<<1))
#define HRQA0 (RQAA+(RQ_WA0<<1))
#define HRQSQ (RQAA+(RQ_WSQ<<1))
#endif
#ifdef EISA
#define DMA_BUSY_CHECK CSRA
#define DMA_HIGH_WORD 0x0400
#define DMA_MASK_M 0x0a
#define DMA_MODE_M 0x0b
#define DMA_BYTE_PTR_M 0x0c
#define DMA_MASK_S 0x0d4
#define DMA_MODE_S 0x0d6
#define DMA_BYTE_PTR_S 0x0d8
#define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TC)
#endif /* EISA */
#ifdef MCA
#define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TOKEN | \
IS_CHCK_L | IS_BUSERR)
#endif
#ifdef PCI
#define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TOKEN | \
IS_MINTR2 | IS_MINTR3 | IS_R1_P | \

33
drivers/net/skfp/h/targethw.h
View File

@ -53,11 +53,6 @@ struct s_oem_ids {
u_char oi_sub_id[4] ; /* sub id bytes, representation as */
/* defined by hardware, */
#endif
#ifdef ISA
u_char oi_logo_len ; /* the length of the adapter logo */
u_char oi_logo[6] ; /* the adapter logo */
u_char oi_reserved1 ;
#endif /* ISA */
} ;
#endif /* MULT_OEM */
@ -70,43 +65,17 @@ struct s_smt_hw {
short dma ; /* DMA channel */
short irq ; /* IRQ level */
short eprom ; /* FLASH prom */
#ifndef PCI
short DmaWriteExtraBytes ; /* add bytes for DMA write */
#endif
#ifndef SYNC
u_short n_a_send ; /* pending send requests */
#endif
#if (defined(EISA) || defined(MCA) || defined(PCI))
#if defined(PCI)
short slot ; /* slot number */
short max_slots ; /* maximum number of slots */
#endif
#if (defined(PCI) || defined(MCA))
short wdog_used ; /* TRUE if the watch dog is used */
#endif
#ifdef MCA
short slot_32 ; /* 32bit slot (1) or 16bit slot (0) */
short rev ; /* Board revision (FMx_REV). */
short VFullRead ; /* V_full value for DMA read */
short VFullWrite ; /* V_full value for DMA write */
#endif
#ifdef EISA
short led ; /* LED for FE card */
short dma_rmode ; /* read mode */
short dma_wmode ; /* write mode */
short dma_emode ; /* extend mode */
/* DMA controller channel dependent io addresses */
u_short dma_base_word_count ;
u_short dma_base_address ;
u_short dma_base_address_page ;
#endif
#ifdef PCI
u_short pci_handle ; /* handle to access the BIOS func */
u_long is_imask ; /* int maske for the int source reg */

42
drivers/net/skfp/hwt.c
View File

@ -77,25 +77,10 @@ void hwt_start(struct s_smc *smc, u_long time)
*/
if (!cnt)
cnt++ ;
#ifndef PCI
/*
* 6.25MHz -> CLK0 : T0 (cnt0 = 16us) -> OUT0
* OUT0 -> CLK1 : T1 (cnt1) OUT1 -> ISRA(IS_TIMINT)
*/
OUT_82c54_TIMER(3,1<<6 | 3<<4 | 0<<1) ; /* counter 1, mode 0 */
OUT_82c54_TIMER(1,cnt & 0xff) ; /* LSB */
OUT_82c54_TIMER(1,(cnt>>8) & 0xff) ; /* MSB */
/*
* start timer by switching counter 0 to mode 3
* T0 resolution 16 us (CLK0=0.16us)
*/
OUT_82c54_TIMER(3,0<<6 | 3<<4 | 3<<1) ; /* counter 0, mode 3 */
OUT_82c54_TIMER(0,100) ; /* LSB */
OUT_82c54_TIMER(0,0) ; /* MSB */
#else /* PCI */
outpd(ADDR(B2_TI_INI), (u_long) cnt * 200) ; /* Load timer value. */
outpw(ADDR(B2_TI_CRTL), TIM_START) ; /* Start timer. */
#endif /* PCI */
smc->hw.timer_activ = TRUE ;
}
@ -115,15 +100,8 @@ void hwt_start(struct s_smc *smc, u_long time)
************************/
void hwt_stop(struct s_smc *smc)
{
#ifndef PCI
/* stop counter 0 by switching to mode 0 */
OUT_82c54_TIMER(3,0<<6 | 3<<4 | 0<<1) ; /* counter 0, mode 0 */
OUT_82c54_TIMER(0,0) ; /* LSB */
OUT_82c54_TIMER(0,0) ; /* MSB */
#else /* PCI */
outpw(ADDR(B2_TI_CRTL), TIM_STOP) ;
outpw(ADDR(B2_TI_CRTL), TIM_CL_IRQ) ;
#endif /* PCI */
smc->hw.timer_activ = FALSE ;
}
@ -168,11 +146,6 @@ void hwt_init(struct s_smc *smc)
void hwt_restart(struct s_smc *smc)
{
hwt_stop(smc) ;
#ifndef PCI
OUT_82c54_TIMER(3,1<<6 | 3<<4 | 0<<1) ; /* counter 1, mode 0 */
OUT_82c54_TIMER(1,1 ) ; /* LSB */
OUT_82c54_TIMER(1,0 ) ; /* MSB */
#endif
}
/************************
@ -191,21 +164,12 @@ void hwt_restart(struct s_smc *smc)
u_long hwt_read(struct s_smc *smc)
{
u_short tr ;
#ifndef PCI
u_short is ;
#else
u_long is ;
#endif
if (smc->hw.timer_activ) {
hwt_stop(smc) ;
#ifndef PCI
OUT_82c54_TIMER(3,1<<6) ; /* latch command */
tr = IN_82c54_TIMER(1) & 0xff ;
tr += (IN_82c54_TIMER(1) & 0xff)<<8 ;
#else /* PCI */
tr = (u_short)((inpd(ADDR(B2_TI_VAL))/200) & 0xffff) ;
#endif /* PCI */
is = GET_ISR() ;
/* Check if timer expired (or wraparound). */
if ((tr > smc->hw.t_start) || (is & IS_TIMINT)) {