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dt-binding: mt8192: add toprgu reset-controller head file 

add toprgu reset-controller head file for MT8192 platform

Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20201014131936.20584-4-crystal.guo@mediatek.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
master
Crystal Guo 2020-10-14 21:19:35 +08:00 committed by Wim Van Sebroeck
parent 53526bef0a
commit af2a30fb70
1 changed files with 30 additions and 0 deletions
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30
include/dt-bindings/reset-controller/mt8192-resets.h 100644
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2020 MediaTek Inc.
* Author: Yong Liang <yong.liang@mediatek.com>
*/
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
#define MT8192_TOPRGU_MM_SW_RST 1
#define MT8192_TOPRGU_MFG_SW_RST 2
#define MT8192_TOPRGU_VENC_SW_RST 3
#define MT8192_TOPRGU_VDEC_SW_RST 4
#define MT8192_TOPRGU_IMG_SW_RST 5
#define MT8192_TOPRGU_MD_SW_RST 7
#define MT8192_TOPRGU_CONN_SW_RST 9
#define MT8192_TOPRGU_CONN_MCU_SW_RST 12
#define MT8192_TOPRGU_IPU0_SW_RST 14
#define MT8192_TOPRGU_IPU1_SW_RST 15
#define MT8192_TOPRGU_AUDIO_SW_RST 17
#define MT8192_TOPRGU_CAMSYS_SW_RST 18
#define MT8192_TOPRGU_MJC_SW_RST 19
#define MT8192_TOPRGU_C2K_S2_SW_RST 20
#define MT8192_TOPRGU_C2K_SW_RST 21
#define MT8192_TOPRGU_PERI_SW_RST 22
#define MT8192_TOPRGU_PERI_AO_SW_RST 23
#define MT8192_TOPRGU_SW_RST_NUM 23
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */