MIPS: ath79: add support for QCA953x QCA956x TP9343
This patch adds support for 2 new types of QCA silicon. TP9343 is essentially the same as the QCA956X but is licensed by TPLink. Signed-off-by: Weijie Gao <hackpascal@gmail.com> Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19911/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.orghifive-unleashed-5.1
Matthias Schiffer
Paul Burton
parent
a95f4b1c28
commit
af2d1b521b
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@ -355,6 +355,91 @@ static void __init ar934x_clocks_init(void)
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iounmap(dpll_base);
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}
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static void __init qca953x_clocks_init(void)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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unsigned long ddr_rate;
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unsigned long ahb_rate;
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u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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u32 cpu_pll, ddr_pll;
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u32 bootstrap;
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bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
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ref_rate = 40 * 1000 * 1000;
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else
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ref_rate = 25 * 1000 * 1000;
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pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
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out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
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nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
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QCA953X_PLL_CPU_CONFIG_NINT_MASK;
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frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
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QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
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cpu_pll = nint * ref_rate / ref_div;
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cpu_pll += frac * (ref_rate >> 6) / ref_div;
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cpu_pll /= (1 << out_div);
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pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
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out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
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nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
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QCA953X_PLL_DDR_CONFIG_NINT_MASK;
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frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
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QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
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ddr_pll = nint * ref_rate / ref_div;
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ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
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ddr_pll /= (1 << out_div);
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clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
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postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
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if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
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cpu_rate = ref_rate;
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else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
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cpu_rate = cpu_pll / (postdiv + 1);
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else
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cpu_rate = ddr_pll / (postdiv + 1);
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postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
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if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
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ddr_rate = ref_rate;
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else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
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ddr_rate = ddr_pll / (postdiv + 1);
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else
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ddr_rate = cpu_pll / (postdiv + 1);
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postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
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if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
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ahb_rate = ref_rate;
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else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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ahb_rate = ddr_pll / (postdiv + 1);
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else
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ahb_rate = cpu_pll / (postdiv + 1);
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ath79_add_sys_clkdev("ref", ref_rate);
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ath79_add_sys_clkdev("cpu", cpu_rate);
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ath79_add_sys_clkdev("ddr", ddr_rate);
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ath79_add_sys_clkdev("ahb", ahb_rate);
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clk_add_alias("wdt", NULL, "ref", NULL);
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clk_add_alias("uart", NULL, "ref", NULL);
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}
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static void __init qca955x_clocks_init(void)
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{
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unsigned long ref_rate;
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@ -440,6 +525,110 @@ static void __init qca955x_clocks_init(void)
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clk_add_alias("uart", NULL, "ref", NULL);
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}
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static void __init qca956x_clocks_init(void)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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unsigned long ddr_rate;
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unsigned long ahb_rate;
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u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
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u32 cpu_pll, ddr_pll;
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u32 bootstrap;
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/*
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* QCA956x timer init workaround has to be applied right before setting
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* up the clock. Else, there will be no jiffies
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*/
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u32 misc;
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misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
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misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
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ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
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bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
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if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
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ref_rate = 40 * 1000 * 1000;
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else
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ref_rate = 25 * 1000 * 1000;
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pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
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out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
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pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
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nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
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QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
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hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
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QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
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lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
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QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
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cpu_pll = nint * ref_rate / ref_div;
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cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
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cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
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cpu_pll /= (1 << out_div);
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pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
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out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
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pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
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nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
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QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
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hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
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QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
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lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
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QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
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ddr_pll = nint * ref_rate / ref_div;
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ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
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ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
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ddr_pll /= (1 << out_div);
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clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
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postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
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if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
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cpu_rate = ref_rate;
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else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
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cpu_rate = ddr_pll / (postdiv + 1);
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else
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cpu_rate = cpu_pll / (postdiv + 1);
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postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
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if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
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ddr_rate = ref_rate;
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else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
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ddr_rate = cpu_pll / (postdiv + 1);
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else
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ddr_rate = ddr_pll / (postdiv + 1);
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postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
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if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
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ahb_rate = ref_rate;
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else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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ahb_rate = ddr_pll / (postdiv + 1);
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else
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ahb_rate = cpu_pll / (postdiv + 1);
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ath79_add_sys_clkdev("ref", ref_rate);
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ath79_add_sys_clkdev("cpu", cpu_rate);
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ath79_add_sys_clkdev("ddr", ddr_rate);
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ath79_add_sys_clkdev("ahb", ahb_rate);
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clk_add_alias("wdt", NULL, "ref", NULL);
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clk_add_alias("uart", NULL, "ref", NULL);
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}
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void __init ath79_clocks_init(void)
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{
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if (soc_is_ar71xx())
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@ -450,8 +639,12 @@ void __init ath79_clocks_init(void)
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ar933x_clocks_init();
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else if (soc_is_ar934x())
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ar934x_clocks_init();
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else if (soc_is_qca953x())
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qca953x_clocks_init();
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else if (soc_is_qca955x())
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qca955x_clocks_init();
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else if (soc_is_qca956x() || soc_is_tp9343())
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qca956x_clocks_init();
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else
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BUG();
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}
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@ -103,8 +103,12 @@ void ath79_device_reset_set(u32 mask)
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca953x())
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reg = QCA953X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca956x() || soc_is_tp9343())
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reg = QCA956X_RESET_REG_RESET_MODULE;
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else
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BUG();
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@ -131,8 +135,12 @@ void ath79_device_reset_clear(u32 mask)
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca953x())
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reg = QCA953X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca956x() || soc_is_tp9343())
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reg = QCA956X_RESET_REG_RESET_MODULE;
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else
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BUG();
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@ -78,8 +78,12 @@ static void prom_putchar_init(void)
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case REV_ID_MAJOR_AR9341:
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case REV_ID_MAJOR_AR9342:
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case REV_ID_MAJOR_AR9344:
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case REV_ID_MAJOR_QCA9533:
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case REV_ID_MAJOR_QCA9533_V2:
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case REV_ID_MAJOR_QCA9556:
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case REV_ID_MAJOR_QCA9558:
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case REV_ID_MAJOR_TP9343:
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case REV_ID_MAJOR_QCA956X:
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_prom_putchar = prom_putchar_ar71xx;
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break;
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@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type(void)
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u32 major;
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u32 minor;
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u32 rev = 0;
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u32 ver = 1;
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id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
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major = id & REV_ID_MAJOR_MASK;
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@ -151,6 +152,17 @@ static void __init ath79_detect_sys_type(void)
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rev = id & AR934X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_QCA9533_V2:
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ver = 2;
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ath79_soc_rev = 2;
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/* drop through */
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case REV_ID_MAJOR_QCA9533:
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ath79_soc = ATH79_SOC_QCA9533;
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chip = "9533";
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rev = id & QCA953X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_QCA9556:
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ath79_soc = ATH79_SOC_QCA9556;
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chip = "9556";
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@ -163,14 +175,30 @@ static void __init ath79_detect_sys_type(void)
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rev = id & QCA955X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_QCA956X:
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ath79_soc = ATH79_SOC_QCA956X;
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chip = "956X";
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rev = id & QCA956X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_TP9343:
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ath79_soc = ATH79_SOC_TP9343;
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chip = "9343";
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rev = id & QCA956X_REV_ID_REVISION_MASK;
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break;
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default:
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panic("ath79: unknown SoC, id:0x%08x", id);
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}
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ath79_soc_rev = rev;
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if (ver == 1)
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ath79_soc_rev = rev;
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if (soc_is_qca955x())
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sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
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if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
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sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
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chip, ver, rev);
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else if (soc_is_tp9343())
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sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
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chip, rev);
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else
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sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
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@ -32,8 +32,11 @@ enum ath79_soc_type {
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ATH79_SOC_AR9341,
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ATH79_SOC_AR9342,
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ATH79_SOC_AR9344,
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ATH79_SOC_QCA9533,
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ATH79_SOC_QCA9556,
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ATH79_SOC_QCA9558,
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ATH79_SOC_TP9343,
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ATH79_SOC_QCA956X,
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};
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extern enum ath79_soc_type ath79_soc;
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@ -100,6 +103,16 @@ static inline int soc_is_ar934x(void)
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return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
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}
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static inline int soc_is_qca9533(void)
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{
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return ath79_soc == ATH79_SOC_QCA9533;
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}
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static inline int soc_is_qca953x(void)
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{
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return soc_is_qca9533();
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}
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static inline int soc_is_qca9556(void)
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{
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return ath79_soc == ATH79_SOC_QCA9556;
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@ -115,6 +128,26 @@ static inline int soc_is_qca955x(void)
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return soc_is_qca9556() || soc_is_qca9558();
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}
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static inline int soc_is_tp9343(void)
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{
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return ath79_soc == ATH79_SOC_TP9343;
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}
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static inline int soc_is_qca9561(void)
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{
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return ath79_soc == ATH79_SOC_QCA956X;
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}
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static inline int soc_is_qca9563(void)
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{
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return ath79_soc == ATH79_SOC_QCA956X;
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}
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static inline int soc_is_qca956x(void)
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{
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return soc_is_qca9561() || soc_is_qca9563();
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}
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void ath79_ddr_wb_flush(unsigned int reg);
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void ath79_ddr_set_pci_windows(void);
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