- arm64: dts: mediatek: add mt6795 support
- Document: DT: Add bindings for mediatek MT6795 SoC Platform - arm64: dts: mediatek: Add MT8173 MMC dts - arm64: dts: mt8173: Add afe device node - arm64: dts: mt8173-evb: Add PMIC support - dts: mt8173-evb: Add da9211 to i2c1 - ARM: dts: mt8173: support arm64 cpuidle-dt - ARM64: MediaTek MT8173: Add SCPSYS device node - arm64: dts: mt8173: Add I2C device node - arm64: dts: mt8173: Add watchdog device node - arm64: dts: mt8173: Add PMIC wrapper device node - arm64: dts: mt8173: Use real clock for UARTs - arm64: dts: mt8173: Add clock controller device nodes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVt2JqAAoJELQ5Ylss8dNDh28P/i+8RDwaK85GgJtC3gYmjTPU JwpNYbzyCD6ObhPQS7arGrn+guyVSrQid95V1YNVQJRufuHGJzRWQ7v0i8p3d144 b3eLOWRF2Tuvx6fDy2sGHiFuWvprtpYvhiM12A8nVllUcV1HpY8nndE3Cffrx8JX RY2o/x62beSzzOnsXny/ye5fqVitMfoNC//b1FB5qnEs8wl+SGW3PVGBPeOsHp6T U+sj4A31lbKtUL5JWsaHIM/cgNrkh3NcuU1cm9p5dBGIqh2ZsuiyHyjrBoERYrbw nNwGlwRPIq/XosnQIr+pjlsJ4yJrYEavord8ve58N4fBD6tmeQFExEP5g1T797px 7tL5Mw7FT95J7s1eYqtV8ZUTdvMZvLGNPGX7sQsPIezpCra9h9i0XaSkCbrsikKY DF0C1vtF86XS+Ki7Oxll5z3PYd1Hv8NUDl/h5o5nnFOXZz6RE2PT6mM+YUPLeA/B An7+GlWYe6lmcprPMNYkhf1ry0srAJKMBi1xAV2DkZKho1qNyvVQIJVEVm7m6yXp DqD8+gBKnbeNOs+s6h/JHDqcHVtoGgnWByMGcUcb86LJwzjKz321GEUBJJ6HMobu vkY379//teNbhJQz3E5BcAiYMKszc1Le8cwLGD+G5tI3toR5GRagJrQV0evS/Py4 q2sLamn1vn03aUEvskkT =RiLC -----END PGP SIGNATURE----- Merge tag 'v4.2-next-arm64' of https://github.com/mbgg/linux-mediatek into next/arm64 - arm64: dts: mediatek: add mt6795 support - Document: DT: Add bindings for mediatek MT6795 SoC Platform - arm64: dts: mediatek: Add MT8173 MMC dts - arm64: dts: mt8173: Add afe device node - arm64: dts: mt8173-evb: Add PMIC support - dts: mt8173-evb: Add da9211 to i2c1 - ARM: dts: mt8173: support arm64 cpuidle-dt - ARM64: MediaTek MT8173: Add SCPSYS device node - arm64: dts: mt8173: Add I2C device node - arm64: dts: mt8173: Add watchdog device node - arm64: dts: mt8173: Add PMIC wrapper device node - arm64: dts: mt8173: Use real clock for UARTs - arm64: dts: mt8173: Add clock controller device nodes * tag 'v4.2-next-arm64' of https://github.com/mbgg/linux-mediatek: arm64: dts: mediatek: add mt6795 support Document: DT: Add bindings for mediatek MT6795 SoC Platform arm64: dts: mediatek: Add MT8173 MMC dts arm64: dts: mt8173: Add afe device node arm64: dts: mt8173-evb: Add PMIC support dts: mt8173-evb: Add da9211 to i2c1 ARM: dts: mt8173: support arm64 cpuidle-dt ARM64: MediaTek MT8173: Add SCPSYS device node arm64: dts: mt8173: Add I2C device node arm64: dts: mt8173: Add watchdog device node arm64: dts: mt8173: Add PMIC wrapper device node arm64: dts: mt8173: Use real clock for UARTs arm64: dts: mt8173: Add clock controller device nodes Signed-off-by: Olof Johansson <olof@lixom.net>hifive-unleashed-5.1
Olof Johansson
commit
af429d9ebf
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@ -1,12 +1,14 @@
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MediaTek mt65xx & mt81xx Platforms Device Tree Bindings
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MediaTek mt65xx, mt67xx & mt81xx Platforms Device Tree Bindings
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Boards with a MediaTek mt65xx/mt81xx SoC shall have the following property:
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Boards with a MediaTek mt65xx/mt67xx/mt81xx SoC shall have the
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following property:
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Required root node property:
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compatible: Must contain one of
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"mediatek,mt6589"
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"mediatek,mt6592"
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"mediatek,mt6795"
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"mediatek,mt8127"
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"mediatek,mt8135"
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"mediatek,mt8173"
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@ -20,6 +22,9 @@ Supported boards:
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- Evaluation board for MT6592:
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Required root node properties:
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- compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
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- Evaluation board for MT6795(Helio X10):
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Required root node properties:
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- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
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- MTK mt8127 tablet moose EVB:
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Required root node properties:
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- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
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@ -1,4 +1,4 @@
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Mediatek 65xx/81xx sysirq
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+Mediatek 65xx/67xx/81xx sysirq
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Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
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interrupt.
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@ -8,6 +8,7 @@ Required properties:
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"mediatek,mt8173-sysirq"
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"mediatek,mt8135-sysirq"
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"mediatek,mt8127-sysirq"
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"mediatek,mt6795-sysirq"
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"mediatek,mt6592-sysirq"
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"mediatek,mt6589-sysirq"
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"mediatek,mt6582-sysirq"
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@ -5,10 +5,11 @@ Required properties:
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* "mediatek,mt8135-uart" for MT8135 compatible UARTS
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* "mediatek,mt8127-uart" for MT8127 compatible UARTS
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* "mediatek,mt8173-uart" for MT8173 compatible UARTS
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* "mediatek,mt6795-uart" for MT6795 compatible UARTS
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* "mediatek,mt6589-uart" for MT6589 compatible UARTS
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* "mediatek,mt6582-uart" for MT6582 compatible UARTS
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* "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6589, MT6582,
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MT6577)
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* "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6795, MT6589,
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MT6582, MT6577)
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- reg: The base address of the UART register bank.
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@ -1,3 +1,4 @@
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
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always := $(dtb-y)
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@ -0,0 +1,41 @@
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/*
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* Copyright (c) 2015 MediaTek Inc.
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* Author: Mars.C <mars.cheng@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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#include "mt6795.dtsi"
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/ {
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model = "MediaTek MT6795 Evaluation Board";
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compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x1e800000>;
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};
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chosen {
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stdout-path = "serial0:921600n8";
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};
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};
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&uart0 {
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status = "okay";
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};
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@ -0,0 +1,162 @@
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/*
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* Copyright (c) 2015 MediaTek Inc.
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* Author: Mars.C <mars.cheng@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "mediatek,mt6795";
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interrupt-parent = <&sysirq>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x001>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x002>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x003>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x102>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x103>;
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};
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};
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system_clk: dummy13m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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};
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rtc_clk: dummy32k {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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uart_clk: dummy26m {
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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#clock-cells = <0>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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sysirq: intpol-controller@10200620 {
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compatible = "mediatek,mt6795-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10200620 0 0x20>;
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};
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gic: interrupt-controller@10221000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x10221000 0 0x1000>,
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<0 0x10222000 0 0x2000>,
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<0 0x10224000 0 0x2000>,
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<0 0x10226000 0 0x2000>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt6795-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt6795-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt6795-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart3: serial@11005000 {
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compatible = "mediatek,mt6795-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11005000 0 0x400>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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};
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@ -34,6 +34,359 @@
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chosen { };
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};
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&i2c1 {
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status = "okay";
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buck: da9211@68 {
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compatible = "dlg,da9211";
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reg = <0x68>;
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regulators {
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da9211_vcpu_reg: BUCKA {
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regulator-name = "VBUCKA";
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regulator-min-microvolt = < 700000>;
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regulator-max-microvolt = <1310000>;
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regulator-min-microamp = <2000000>;
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regulator-max-microamp = <4400000>;
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regulator-ramp-delay = <10000>;
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regulator-always-on;
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};
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da9211_vgpu_reg: BUCKB {
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regulator-name = "VBUCKB";
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regulator-min-microvolt = < 700000>;
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regulator-max-microvolt = <1310000>;
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regulator-min-microamp = <2000000>;
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regulator-max-microamp = <3000000>;
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regulator-ramp-delay = <10000>;
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};
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};
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};
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};
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&mmc0 {
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status = "okay";
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&mmc0_pins_default>;
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pinctrl-1 = <&mmc0_pins_uhs>;
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bus-width = <8>;
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max-frequency = <50000000>;
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cap-mmc-highspeed;
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vmmc-supply = <&mt6397_vemc_3v3_reg>;
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vqmmc-supply = <&mt6397_vio18_reg>;
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non-removable;
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};
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&mmc1 {
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status = "okay";
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&mmc1_pins_default>;
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pinctrl-1 = <&mmc1_pins_uhs>;
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bus-width = <4>;
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max-frequency = <50000000>;
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cap-sd-highspeed;
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sd-uhs-sdr25;
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cd-gpios = <&pio 132 0>;
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vmmc-supply = <&mt6397_vmch_reg>;
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vqmmc-supply = <&mt6397_vmc_reg>;
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};
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&pio {
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mmc0_pins_default: mmc0default {
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pins_cmd_dat {
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pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
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<MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
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<MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
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<MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
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<MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
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<MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
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<MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
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<MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
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<MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
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input-enable;
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bias-pull-up;
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};
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pins_clk {
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pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
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bias-pull-down;
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};
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pins_rst {
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pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
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bias-pull-up;
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};
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};
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mmc1_pins_default: mmc1default {
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pins_cmd_dat {
|
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pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
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<MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
|
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<MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
|
||||
<MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
|
||||
<MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
|
||||
input-enable;
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
pins_clk {
|
||||
pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
|
||||
bias-pull-down;
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
};
|
||||
|
||||
pins_insert {
|
||||
pinmux = <MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_pins_uhs: mmc0 {
|
||||
pins_cmd_dat {
|
||||
pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
|
||||
<MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
|
||||
<MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
|
||||
<MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
|
||||
<MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
|
||||
<MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
|
||||
<MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
|
||||
<MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
|
||||
<MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
|
||||
input-enable;
|
||||
drive-strength = <MTK_DRIVE_2mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
|
||||
pins_clk {
|
||||
pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
|
||||
drive-strength = <MTK_DRIVE_2mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
|
||||
pins_rst {
|
||||
pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mmc1_pins_uhs: mmc1 {
|
||||
pins_cmd_dat {
|
||||
pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
|
||||
<MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
|
||||
<MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
|
||||
<MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
|
||||
<MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
|
||||
input-enable;
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
pins_clk {
|
||||
pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwrap {
|
||||
pmic: mt6397 {
|
||||
compatible = "mediatek,mt6397";
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
mt6397regulator: mt6397regulator {
|
||||
compatible = "mediatek,mt6397-regulator";
|
||||
|
||||
mt6397_vpca15_reg: buck_vpca15 {
|
||||
regulator-compatible = "buck_vpca15";
|
||||
regulator-name = "vpca15";
|
||||
regulator-min-microvolt = < 700000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
mt6397_vpca7_reg: buck_vpca7 {
|
||||
regulator-compatible = "buck_vpca7";
|
||||
regulator-name = "vpca7";
|
||||
regulator-min-microvolt = < 700000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-enable-ramp-delay = <115>;
|
||||
};
|
||||
|
||||
mt6397_vsramca15_reg: buck_vsramca15 {
|
||||
regulator-compatible = "buck_vsramca15";
|
||||
regulator-name = "vsramca15";
|
||||
regulator-min-microvolt = < 700000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
mt6397_vsramca7_reg: buck_vsramca7 {
|
||||
regulator-compatible = "buck_vsramca7";
|
||||
regulator-name = "vsramca7";
|
||||
regulator-min-microvolt = < 700000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
mt6397_vcore_reg: buck_vcore {
|
||||
regulator-compatible = "buck_vcore";
|
||||
regulator-name = "vcore";
|
||||
regulator-min-microvolt = < 700000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
mt6397_vgpu_reg: buck_vgpu {
|
||||
regulator-compatible = "buck_vgpu";
|
||||
regulator-name = "vgpu";
|
||||
regulator-min-microvolt = < 700000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-enable-ramp-delay = <115>;
|
||||
};
|
||||
|
||||
mt6397_vdrm_reg: buck_vdrm {
|
||||
regulator-compatible = "buck_vdrm";
|
||||
regulator-name = "vdrm";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
mt6397_vio18_reg: buck_vio18 {
|
||||
regulator-compatible = "buck_vio18";
|
||||
regulator-name = "vio18";
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <1980000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
mt6397_vtcxo_reg: ldo_vtcxo {
|
||||
regulator-compatible = "ldo_vtcxo";
|
||||
regulator-name = "vtcxo";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
mt6397_va28_reg: ldo_va28 {
|
||||
regulator-compatible = "ldo_va28";
|
||||
regulator-name = "va28";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
mt6397_vcama_reg: ldo_vcama {
|
||||
regulator-compatible = "ldo_vcama";
|
||||
regulator-name = "vcama";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-enable-ramp-delay = <218>;
|
||||
};
|
||||
|
||||
mt6397_vio28_reg: ldo_vio28 {
|
||||
regulator-compatible = "ldo_vio28";
|
||||
regulator-name = "vio28";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
mt6397_vusb_reg: ldo_vusb {
|
||||
regulator-compatible = "ldo_vusb";
|
||||
regulator-name = "vusb";
|
||||
};
|
||||
|
||||
mt6397_vmc_reg: ldo_vmc {
|
||||
regulator-compatible = "ldo_vmc";
|
||||
regulator-name = "vmc";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-enable-ramp-delay = <218>;
|
||||
};
|
||||
|
||||
mt6397_vmch_reg: ldo_vmch {
|
||||
regulator-compatible = "ldo_vmch";
|
||||
regulator-name = "vmch";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-enable-ramp-delay = <218>;
|
||||
};
|
||||
|
||||
mt6397_vemc_3v3_reg: ldo_vemc3v3 {
|
||||
regulator-compatible = "ldo_vemc3v3";
|
||||
regulator-name = "vemc_3v3";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-enable-ramp-delay = <218>;
|
||||
};
|
||||
|
||||
mt6397_vgp1_reg: ldo_vgp1 {
|
||||
regulator-compatible = "ldo_vgp1";
|
||||
regulator-name = "vcamd";
|
||||
regulator-min-microvolt = <1220000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-enable-ramp-delay = <240>;
|
||||
};
|
||||
|
||||
mt6397_vgp2_reg: ldo_vgp2 {
|
||||
regulator-compatible = "ldo_vgp2";
|
||||
regulator-name = "vcamio";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-enable-ramp-delay = <218>;
|
||||
};
|
||||
|
||||
mt6397_vgp3_reg: ldo_vgp3 {
|
||||
regulator-compatible = "ldo_vgp3";
|
||||
regulator-name = "vcamaf";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-enable-ramp-delay = <218>;
|
||||
};
|
||||
|
||||
mt6397_vgp4_reg: ldo_vgp4 {
|
||||
regulator-compatible = "ldo_vgp4";
|
||||
regulator-name = "vgp4";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-enable-ramp-delay = <218>;
|
||||
};
|
||||
|
||||
mt6397_vgp5_reg: ldo_vgp5 {
|
||||
regulator-compatible = "ldo_vgp5";
|
||||
regulator-name = "vgp5";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-enable-ramp-delay = <218>;
|
||||
};
|
||||
|
||||
mt6397_vgp6_reg: ldo_vgp6 {
|
||||
regulator-compatible = "ldo_vgp6";
|
||||
regulator-name = "vgp6";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-enable-ramp-delay = <218>;
|
||||
};
|
||||
|
||||
mt6397_vibr_reg: ldo_vibr {
|
||||
regulator-compatible = "ldo_vibr";
|
||||
regulator-name = "vibr";
|
||||
regulator-min-microvolt = <1300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-enable-ramp-delay = <218>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -11,8 +11,11 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/mt8173-power.h>
|
||||
#include <dt-bindings/reset-controller/mt8173-resets.h>
|
||||
#include "mt8173-pinfunc.h"
|
||||
|
||||
/ {
|
||||
|
|
@ -49,6 +52,8 @@
|
|||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
|
|
@ -56,6 +61,7 @@
|
|||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu2: cpu@100 {
|
||||
|
|
@ -63,6 +69,7 @@
|
|||
compatible = "arm,cortex-a57";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu3: cpu@101 {
|
||||
|
|
@ -70,6 +77,20 @@
|
|||
compatible = "arm,cortex-a57";
|
||||
reg = <0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "arm,psci";
|
||||
|
||||
CPU_SLEEP_0: cpu-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <639>;
|
||||
exit-latency-us = <680>;
|
||||
min-residency-us = <1088>;
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -81,10 +102,18 @@
|
|||
cpu_on = <0x84000003>;
|
||||
};
|
||||
|
||||
uart_clk: dummy26m {
|
||||
clk26m: oscillator@0 {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
clock-output-names = "clk26m";
|
||||
};
|
||||
|
||||
clk32k: oscillator@1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32000>;
|
||||
clock-output-names = "clk32k";
|
||||
};
|
||||
|
||||
timer {
|
||||
|
|
@ -106,11 +135,32 @@
|
|||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
/*
|
||||
* Pinctrl access register at 0x10005000 through regmap.
|
||||
* Register 0x1000b000 is used by EINT.
|
||||
*/
|
||||
pio: pinctrl@10005000 {
|
||||
topckgen: clock-controller@10000000 {
|
||||
compatible = "mediatek,mt8173-topckgen";
|
||||
reg = <0 0x10000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
infracfg: power-controller@10001000 {
|
||||
compatible = "mediatek,mt8173-infracfg", "syscon";
|
||||
reg = <0 0x10001000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
pericfg: power-controller@10003000 {
|
||||
compatible = "mediatek,mt8173-pericfg", "syscon";
|
||||
reg = <0 0x10003000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
syscfg_pctl_a: syscfg_pctl_a@10005000 {
|
||||
compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
|
||||
reg = <0 0x10005000 0 0x1000>;
|
||||
};
|
||||
|
||||
pio: pinctrl@0x10005000 {
|
||||
compatible = "mediatek,mt8173-pinctrl";
|
||||
reg = <0 0x1000b000 0 0x1000>;
|
||||
mediatek,pctl-regmap = <&syscfg_pctl_a>;
|
||||
|
|
@ -122,11 +172,81 @@
|
|||
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
i2c0_pins_a: i2c0 {
|
||||
pins1 {
|
||||
pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
|
||||
<MT8173_PIN_46_SCL0__FUNC_SCL0>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins_a: i2c1 {
|
||||
pins1 {
|
||||
pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
|
||||
<MT8173_PIN_126_SCL1__FUNC_SCL1>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2_pins_a: i2c2 {
|
||||
pins1 {
|
||||
pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
|
||||
<MT8173_PIN_44_SCL2__FUNC_SCL2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3_pins_a: i2c3 {
|
||||
pins1 {
|
||||
pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
|
||||
<MT8173_PIN_107_SCL3__FUNC_SCL3>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins_a: i2c4 {
|
||||
pins1 {
|
||||
pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
|
||||
<MT8173_PIN_134_SCL4__FUNC_SCL4>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c6_pins_a: i2c6 {
|
||||
pins1 {
|
||||
pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
|
||||
<MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
syscfg_pctl_a: syscfg_pctl_a@10005000 {
|
||||
compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
|
||||
reg = <0 0x10005000 0 0x1000>;
|
||||
scpsys: scpsys@10006000 {
|
||||
compatible = "mediatek,mt8173-scpsys";
|
||||
#power-domain-cells = <1>;
|
||||
reg = <0 0x10006000 0 0x1000>;
|
||||
clocks = <&clk26m>,
|
||||
<&topckgen CLK_TOP_MM_SEL>;
|
||||
clock-names = "mfg", "mm";
|
||||
infracfg = <&infracfg>;
|
||||
};
|
||||
|
||||
watchdog: watchdog@10007000 {
|
||||
compatible = "mediatek,mt8173-wdt",
|
||||
"mediatek,mt6589-wdt";
|
||||
reg = <0 0x10007000 0 0x100>;
|
||||
};
|
||||
|
||||
pwrap: pwrap@1000d000 {
|
||||
compatible = "mediatek,mt8173-pwrap";
|
||||
reg = <0 0x1000d000 0 0x1000>;
|
||||
reg-names = "pwrap";
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
|
||||
reset-names = "pwrap";
|
||||
clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
|
||||
clock-names = "spi", "wrap";
|
||||
};
|
||||
|
||||
sysirq: intpol-controller@10200620 {
|
||||
|
|
@ -138,6 +258,12 @@
|
|||
reg = <0 0x10200620 0 0x20>;
|
||||
};
|
||||
|
||||
apmixedsys: clock-controller@10209000 {
|
||||
compatible = "mediatek,mt8173-apmixedsys";
|
||||
reg = <0 0x10209000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@10220000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -156,7 +282,8 @@
|
|||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11002000 0 0x400>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&uart_clk>;
|
||||
clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
|
||||
clock-names = "baud", "bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -165,7 +292,8 @@
|
|||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11003000 0 0x400>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&uart_clk>;
|
||||
clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
|
||||
clock-names = "baud", "bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -174,7 +302,8 @@
|
|||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11004000 0 0x400>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&uart_clk>;
|
||||
clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
|
||||
clock-names = "baud", "bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -183,7 +312,179 @@
|
|||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11005000 0 0x400>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&uart_clk>;
|
||||
clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
|
||||
clock-names = "baud", "bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11007000 {
|
||||
compatible = "mediatek,mt8173-i2c";
|
||||
reg = <0 0x11007000 0 0x70>,
|
||||
<0 0x11000100 0 0x80>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <16>;
|
||||
clocks = <&pericfg CLK_PERI_I2C0>,
|
||||
<&pericfg CLK_PERI_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins_a>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@11008000 {
|
||||
compatible = "mediatek,mt8173-i2c";
|
||||
reg = <0 0x11008000 0 0x70>,
|
||||
<0 0x11000180 0 0x80>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <16>;
|
||||
clocks = <&pericfg CLK_PERI_I2C1>,
|
||||
<&pericfg CLK_PERI_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins_a>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@11009000 {
|
||||
compatible = "mediatek,mt8173-i2c";
|
||||
reg = <0 0x11009000 0 0x70>,
|
||||
<0 0x11000200 0 0x80>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <16>;
|
||||
clocks = <&pericfg CLK_PERI_I2C2>,
|
||||
<&pericfg CLK_PERI_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_pins_a>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c3@11010000 {
|
||||
compatible = "mediatek,mt8173-i2c";
|
||||
reg = <0 0x11010000 0 0x70>,
|
||||
<0 0x11000280 0 0x80>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <16>;
|
||||
clocks = <&pericfg CLK_PERI_I2C3>,
|
||||
<&pericfg CLK_PERI_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_pins_a>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c4@11011000 {
|
||||
compatible = "mediatek,mt8173-i2c";
|
||||
reg = <0 0x11011000 0 0x70>,
|
||||
<0 0x11000300 0 0x80>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <16>;
|
||||
clocks = <&pericfg CLK_PERI_I2C4>,
|
||||
<&pericfg CLK_PERI_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_pins_a>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c6@11013000 {
|
||||
compatible = "mediatek,mt8173-i2c";
|
||||
reg = <0 0x11013000 0 0x70>,
|
||||
<0 0x11000080 0 0x80>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <16>;
|
||||
clocks = <&pericfg CLK_PERI_I2C6>,
|
||||
<&pericfg CLK_PERI_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c6_pins_a>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
afe: audio-controller@11220000 {
|
||||
compatible = "mediatek,mt8173-afe-pcm";
|
||||
reg = <0 0x11220000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
|
||||
clocks = <&infracfg CLK_INFRA_AUDIO>,
|
||||
<&topckgen CLK_TOP_AUDIO_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_INTBUS_SEL>,
|
||||
<&topckgen CLK_TOP_APLL1_DIV0>,
|
||||
<&topckgen CLK_TOP_APLL2_DIV0>,
|
||||
<&topckgen CLK_TOP_I2S0_M_SEL>,
|
||||
<&topckgen CLK_TOP_I2S1_M_SEL>,
|
||||
<&topckgen CLK_TOP_I2S2_M_SEL>,
|
||||
<&topckgen CLK_TOP_I2S3_M_SEL>,
|
||||
<&topckgen CLK_TOP_I2S3_B_SEL>;
|
||||
clock-names = "infra_sys_audio_clk",
|
||||
"top_pdn_audio",
|
||||
"top_pdn_aud_intbus",
|
||||
"bck0",
|
||||
"bck1",
|
||||
"i2s0_m",
|
||||
"i2s1_m",
|
||||
"i2s2_m",
|
||||
"i2s3_m",
|
||||
"i2s3_b";
|
||||
assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_2_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
|
||||
<&topckgen CLK_TOP_APLL2>;
|
||||
};
|
||||
|
||||
mmc0: mmc@11230000 {
|
||||
compatible = "mediatek,mt8173-mmc",
|
||||
"mediatek,mt8135-mmc";
|
||||
reg = <0 0x11230000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_MSDC30_0>,
|
||||
<&topckgen CLK_TOP_MSDC50_0_H_SEL>;
|
||||
clock-names = "source", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc1: mmc@11240000 {
|
||||
compatible = "mediatek,mt8173-mmc",
|
||||
"mediatek,mt8135-mmc";
|
||||
reg = <0 0x11240000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_MSDC30_1>,
|
||||
<&topckgen CLK_TOP_AXI_SEL>;
|
||||
clock-names = "source", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc2: mmc@11250000 {
|
||||
compatible = "mediatek,mt8173-mmc",
|
||||
"mediatek,mt8135-mmc";
|
||||
reg = <0 0x11250000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_MSDC30_2>,
|
||||
<&topckgen CLK_TOP_AXI_SEL>;
|
||||
clock-names = "source", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc3: mmc@11260000 {
|
||||
compatible = "mediatek,mt8173-mmc",
|
||||
"mediatek,mt8135-mmc";
|
||||
reg = <0 0x11260000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_MSDC30_3>,
|
||||
<&topckgen CLK_TOP_MSDC50_2_H_SEL>;
|
||||
clock-names = "source", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue