powerpc/64s: Consolidate Machine Check 0x200 interrupt
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>hifive-unleashed-5.1
Nicholas Piggin
Michael Ellerman
parent
582baf44f9
commit
afcf009548
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@ -218,6 +218,301 @@ FTR_SECTION_ELSE
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b machine_check_pSeries_0
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
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EXC_REAL_END(machine_check, 0x200, 0x300)
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EXC_VIRT_NONE(0x4200, 0x4300)
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TRAMP_REAL_BEGIN(machine_check_powernv_early)
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BEGIN_FTR_SECTION
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EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
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/*
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* Register contents:
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* R13 = PACA
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* R9 = CR
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* Original R9 to R13 is saved on PACA_EXMC
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*
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* Switch to mc_emergency stack and handle re-entrancy (we limit
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* the nested MCE upto level 4 to avoid stack overflow).
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* Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
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*
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* We use paca->in_mce to check whether this is the first entry or
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* nested machine check. We increment paca->in_mce to track nested
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* machine checks.
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*
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* If this is the first entry then set stack pointer to
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* paca->mc_emergency_sp, otherwise r1 is already pointing to
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* stack frame on mc_emergency stack.
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*
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* NOTE: We are here with MSR_ME=0 (off), which means we risk a
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* checkstop if we get another machine check exception before we do
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* rfid with MSR_ME=1.
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*/
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mr r11,r1 /* Save r1 */
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lhz r10,PACA_IN_MCE(r13)
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cmpwi r10,0 /* Are we in nested machine check */
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bne 0f /* Yes, we are. */
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/* First machine check entry */
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ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
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0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
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addi r10,r10,1 /* increment paca->in_mce */
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sth r10,PACA_IN_MCE(r13)
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/* Limit nested MCE to level 4 to avoid stack overflow */
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cmpwi r10,4
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bgt 2f /* Check if we hit limit of 4 */
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std r11,GPR1(r1) /* Save r1 on the stack. */
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std r11,0(r1) /* make stack chain pointer */
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mfspr r11,SPRN_SRR0 /* Save SRR0 */
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std r11,_NIP(r1)
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mfspr r11,SPRN_SRR1 /* Save SRR1 */
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std r11,_MSR(r1)
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mfspr r11,SPRN_DAR /* Save DAR */
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std r11,_DAR(r1)
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mfspr r11,SPRN_DSISR /* Save DSISR */
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std r11,_DSISR(r1)
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std r9,_CCR(r1) /* Save CR in stackframe */
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/* Save r9 through r13 from EXMC save area to stack frame. */
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EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
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mfmsr r11 /* get MSR value */
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ori r11,r11,MSR_ME /* turn on ME bit */
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ori r11,r11,MSR_RI /* turn on RI bit */
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LOAD_HANDLER(r12, machine_check_handle_early)
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1: mtspr SPRN_SRR0,r12
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mtspr SPRN_SRR1,r11
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rfid
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b . /* prevent speculative execution */
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2:
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/* Stack overflow. Stay on emergency stack and panic.
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* Keep the ME bit off while panic-ing, so that if we hit
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* another machine check we checkstop.
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*/
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addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
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ld r11,PACAKMSR(r13)
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LOAD_HANDLER(r12, unrecover_mce)
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li r10,MSR_ME
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andc r11,r11,r10 /* Turn off MSR_ME */
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b 1b
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b . /* prevent speculative execution */
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END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
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TRAMP_REAL_BEGIN(machine_check_pSeries)
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.globl machine_check_fwnmi
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machine_check_fwnmi:
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SET_SCRATCH0(r13) /* save r13 */
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EXCEPTION_PROLOG_0(PACA_EXMC)
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machine_check_pSeries_0:
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EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200)
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/*
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* The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the
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* difference that MSR_RI is not enabled, because PACA_EXMC is being
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* used, so nested machine check corrupts it. machine_check_common
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* enables MSR_RI.
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*/
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ld r10,PACAKMSR(r13)
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xori r10,r10,MSR_RI
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mfspr r11,SPRN_SRR0
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LOAD_HANDLER(r12, machine_check_common)
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mtspr SPRN_SRR0,r12
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mfspr r12,SPRN_SRR1
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mtspr SPRN_SRR1,r10
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rfid
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b . /* prevent speculative execution */
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TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
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EXC_COMMON_BEGIN(machine_check_common)
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/*
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* Machine check is different because we use a different
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* save area: PACA_EXMC instead of PACA_EXGEN.
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*/
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mfspr r10,SPRN_DAR
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std r10,PACA_EXMC+EX_DAR(r13)
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mfspr r10,SPRN_DSISR
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stw r10,PACA_EXMC+EX_DSISR(r13)
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EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
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FINISH_NAP
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RECONCILE_IRQ_STATE(r10, r11)
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ld r3,PACA_EXMC+EX_DAR(r13)
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lwz r4,PACA_EXMC+EX_DSISR(r13)
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/* Enable MSR_RI when finished with PACA_EXMC */
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li r10,MSR_RI
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mtmsrd r10,1
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std r3,_DAR(r1)
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std r4,_DSISR(r1)
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bl save_nvgprs
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl machine_check_exception
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b ret_from_except
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#define MACHINE_CHECK_HANDLER_WINDUP \
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/* Clear MSR_RI before setting SRR0 and SRR1. */\
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li r0,MSR_RI; \
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mfmsr r9; /* get MSR value */ \
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andc r9,r9,r0; \
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mtmsrd r9,1; /* Clear MSR_RI */ \
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/* Move original SRR0 and SRR1 into the respective regs */ \
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ld r9,_MSR(r1); \
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mtspr SPRN_SRR1,r9; \
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ld r3,_NIP(r1); \
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mtspr SPRN_SRR0,r3; \
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ld r9,_CTR(r1); \
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mtctr r9; \
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ld r9,_XER(r1); \
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mtxer r9; \
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ld r9,_LINK(r1); \
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mtlr r9; \
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REST_GPR(0, r1); \
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REST_8GPRS(2, r1); \
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REST_GPR(10, r1); \
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ld r11,_CCR(r1); \
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mtcr r11; \
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/* Decrement paca->in_mce. */ \
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lhz r12,PACA_IN_MCE(r13); \
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subi r12,r12,1; \
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sth r12,PACA_IN_MCE(r13); \
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REST_GPR(11, r1); \
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REST_2GPRS(12, r1); \
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/* restore original r1. */ \
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ld r1,GPR1(r1)
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/*
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* Handle machine check early in real mode. We come here with
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* ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
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*/
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EXC_COMMON_BEGIN(machine_check_handle_early)
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std r0,GPR0(r1) /* Save r0 */
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EXCEPTION_PROLOG_COMMON_3(0x200)
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bl save_nvgprs
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl machine_check_early
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std r3,RESULT(r1) /* Save result */
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ld r12,_MSR(r1)
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#ifdef CONFIG_PPC_P7_NAP
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/*
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* Check if thread was in power saving mode. We come here when any
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* of the following is true:
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* a. thread wasn't in power saving mode
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* b. thread was in power saving mode with no state loss,
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* supervisor state loss or hypervisor state loss.
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*
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* Go back to nap/sleep/winkle mode again if (b) is true.
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*/
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rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */
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beq 4f /* No, it wasn;t */
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/* Thread was in power saving mode. Go back to nap again. */
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cmpwi r11,2
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blt 3f
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/* Supervisor/Hypervisor state loss */
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li r0,1
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stb r0,PACA_NAPSTATELOST(r13)
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3: bl machine_check_queue_event
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MACHINE_CHECK_HANDLER_WINDUP
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GET_PACA(r13)
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ld r1,PACAR1(r13)
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/*
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* Check what idle state this CPU was in and go back to same mode
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* again.
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*/
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lbz r3,PACA_THREAD_IDLE_STATE(r13)
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cmpwi r3,PNV_THREAD_NAP
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bgt 10f
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IDLE_STATE_ENTER_SEQ(PPC_NAP)
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/* No return */
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10:
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cmpwi r3,PNV_THREAD_SLEEP
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bgt 2f
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IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
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/* No return */
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2:
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/*
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* Go back to winkle. Please note that this thread was woken up in
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* machine check from winkle and have not restored the per-subcore
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* state. Hence before going back to winkle, set last bit of HSPGR0
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* to 1. This will make sure that if this thread gets woken up
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* again at reset vector 0x100 then it will get chance to restore
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* the subcore state.
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*/
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ori r13,r13,1
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SET_PACA(r13)
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IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
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/* No return */
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4:
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#endif
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/*
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* Check if we are coming from hypervisor userspace. If yes then we
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* continue in host kernel in V mode to deliver the MC event.
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*/
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rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */
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beq 5f
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andi. r11,r12,MSR_PR /* See if coming from user. */
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bne 9f /* continue in V mode if we are. */
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5:
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#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
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/*
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* We are coming from kernel context. Check if we are coming from
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* guest. if yes, then we can continue. We will fall through
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* do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
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*/
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lbz r11,HSTATE_IN_GUEST(r13)
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cmpwi r11,0 /* Check if coming from guest */
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bne 9f /* continue if we are. */
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#endif
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/*
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* At this point we are not sure about what context we come from.
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* Queue up the MCE event and return from the interrupt.
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* But before that, check if this is an un-recoverable exception.
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* If yes, then stay on emergency stack and panic.
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*/
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andi. r11,r12,MSR_RI
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bne 2f
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1: mfspr r11,SPRN_SRR0
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LOAD_HANDLER(r10,unrecover_mce)
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mtspr SPRN_SRR0,r10
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ld r10,PACAKMSR(r13)
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/*
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* We are going down. But there are chances that we might get hit by
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* another MCE during panic path and we may run into unstable state
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* with no way out. Hence, turn ME bit off while going down, so that
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* when another MCE is hit during panic path, system will checkstop
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* and hypervisor will get restarted cleanly by SP.
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*/
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li r3,MSR_ME
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andc r10,r10,r3 /* Turn off MSR_ME */
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mtspr SPRN_SRR1,r10
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rfid
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b .
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2:
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/*
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* Check if we have successfully handled/recovered from error, if not
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* then stay on emergency stack and panic.
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*/
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ld r3,RESULT(r1) /* Load result */
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cmpdi r3,0 /* see if we handled MCE successfully */
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beq 1b /* if !handled then panic */
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/*
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* Return from MC interrupt.
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* Queue up the MCE event so that we can log it later, while
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* returning from kernel or opal call.
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*/
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bl machine_check_queue_event
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MACHINE_CHECK_HANDLER_WINDUP
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rfid
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9:
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/* Deliver the machine check to host kernel in V mode. */
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MACHINE_CHECK_HANDLER_WINDUP
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b machine_check_pSeries
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EXC_COMMON_BEGIN(unrecover_mce)
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/* Invoke machine_check_exception to print MCE event and panic. */
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl machine_check_exception
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/*
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* We will not reach here. Even if we did, there is no way out. Call
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* unrecoverable_exception and die.
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*/
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1: addi r3,r1,STACK_FRAME_OVERHEAD
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bl unrecoverable_exception
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b 1b
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EXC_REAL(data_access, 0x300, 0x380)
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@ -425,103 +720,6 @@ EXC_REAL_NONE(0x1800, 0x1900)
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/*** Out of line interrupts support ***/
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/* moved from 0x200 */
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TRAMP_REAL_BEGIN(machine_check_powernv_early)
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BEGIN_FTR_SECTION
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EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
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/*
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* Register contents:
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* R13 = PACA
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* R9 = CR
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* Original R9 to R13 is saved on PACA_EXMC
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*
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* Switch to mc_emergency stack and handle re-entrancy (we limit
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* the nested MCE upto level 4 to avoid stack overflow).
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* Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
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*
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* We use paca->in_mce to check whether this is the first entry or
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* nested machine check. We increment paca->in_mce to track nested
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* machine checks.
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*
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* If this is the first entry then set stack pointer to
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* paca->mc_emergency_sp, otherwise r1 is already pointing to
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* stack frame on mc_emergency stack.
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*
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* NOTE: We are here with MSR_ME=0 (off), which means we risk a
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* checkstop if we get another machine check exception before we do
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* rfid with MSR_ME=1.
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*/
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mr r11,r1 /* Save r1 */
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lhz r10,PACA_IN_MCE(r13)
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cmpwi r10,0 /* Are we in nested machine check */
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bne 0f /* Yes, we are. */
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/* First machine check entry */
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ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
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0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
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addi r10,r10,1 /* increment paca->in_mce */
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sth r10,PACA_IN_MCE(r13)
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/* Limit nested MCE to level 4 to avoid stack overflow */
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cmpwi r10,4
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bgt 2f /* Check if we hit limit of 4 */
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std r11,GPR1(r1) /* Save r1 on the stack. */
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std r11,0(r1) /* make stack chain pointer */
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mfspr r11,SPRN_SRR0 /* Save SRR0 */
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std r11,_NIP(r1)
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mfspr r11,SPRN_SRR1 /* Save SRR1 */
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std r11,_MSR(r1)
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mfspr r11,SPRN_DAR /* Save DAR */
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std r11,_DAR(r1)
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mfspr r11,SPRN_DSISR /* Save DSISR */
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std r11,_DSISR(r1)
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std r9,_CCR(r1) /* Save CR in stackframe */
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/* Save r9 through r13 from EXMC save area to stack frame. */
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EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
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mfmsr r11 /* get MSR value */
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ori r11,r11,MSR_ME /* turn on ME bit */
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ori r11,r11,MSR_RI /* turn on RI bit */
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LOAD_HANDLER(r12, machine_check_handle_early)
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1: mtspr SPRN_SRR0,r12
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mtspr SPRN_SRR1,r11
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rfid
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b . /* prevent speculative execution */
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2:
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/* Stack overflow. Stay on emergency stack and panic.
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* Keep the ME bit off while panic-ing, so that if we hit
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* another machine check we checkstop.
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*/
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addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
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ld r11,PACAKMSR(r13)
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LOAD_HANDLER(r12, unrecover_mce)
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li r10,MSR_ME
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andc r11,r11,r10 /* Turn off MSR_ME */
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b 1b
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b . /* prevent speculative execution */
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END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
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TRAMP_REAL_BEGIN(machine_check_pSeries)
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.globl machine_check_fwnmi
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machine_check_fwnmi:
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SET_SCRATCH0(r13) /* save r13 */
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EXCEPTION_PROLOG_0(PACA_EXMC)
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machine_check_pSeries_0:
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EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200)
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/*
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* The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the
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* difference that MSR_RI is not enabled, because PACA_EXMC is being
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* used, so nested machine check corrupts it. machine_check_common
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* enables MSR_RI.
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*/
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ld r10,PACAKMSR(r13)
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xori r10,r10,MSR_RI
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mfspr r11,SPRN_SRR0
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LOAD_HANDLER(r12, machine_check_common)
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mtspr SPRN_SRR0,r12
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mfspr r12,SPRN_SRR1
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mtspr SPRN_SRR1,r10
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rfid
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b . /* prevent speculative execution */
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TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
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TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
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TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
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TRAMP_KVM(PACA_EXGEN, 0x400)
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@ -791,7 +989,6 @@ EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
|
|||
* only has extra guff for STAB-based processors -- which never
|
||||
* come here.
|
||||
*/
|
||||
EXC_VIRT_NONE(0x4200, 0x4300)
|
||||
|
||||
EXC_VIRT(data_access, 0x4300, 0x4380, 0x300)
|
||||
|
||||
|
|
@ -971,30 +1168,6 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
|
|||
|
||||
EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
|
||||
|
||||
/*
|
||||
* Machine check is different because we use a different
|
||||
* save area: PACA_EXMC instead of PACA_EXGEN.
|
||||
*/
|
||||
EXC_COMMON_BEGIN(machine_check_common)
|
||||
mfspr r10,SPRN_DAR
|
||||
std r10,PACA_EXMC+EX_DAR(r13)
|
||||
mfspr r10,SPRN_DSISR
|
||||
stw r10,PACA_EXMC+EX_DSISR(r13)
|
||||
EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
|
||||
FINISH_NAP
|
||||
RECONCILE_IRQ_STATE(r10, r11)
|
||||
ld r3,PACA_EXMC+EX_DAR(r13)
|
||||
lwz r4,PACA_EXMC+EX_DSISR(r13)
|
||||
/* Enable MSR_RI when finished with PACA_EXMC */
|
||||
li r10,MSR_RI
|
||||
mtmsrd r10,1
|
||||
std r3,_DAR(r1)
|
||||
std r4,_DSISR(r1)
|
||||
bl save_nvgprs
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
bl machine_check_exception
|
||||
b ret_from_except
|
||||
|
||||
EXC_COMMON_BEGIN(alignment_common)
|
||||
mfspr r10,SPRN_DAR
|
||||
std r10,PACA_EXGEN+EX_DAR(r13)
|
||||
|
|
@ -1195,180 +1368,6 @@ hmi_exception_after_realmode:
|
|||
EXCEPTION_PROLOG_0(PACA_EXGEN)
|
||||
b tramp_real_hmi_exception
|
||||
|
||||
|
||||
#define MACHINE_CHECK_HANDLER_WINDUP \
|
||||
/* Clear MSR_RI before setting SRR0 and SRR1. */\
|
||||
li r0,MSR_RI; \
|
||||
mfmsr r9; /* get MSR value */ \
|
||||
andc r9,r9,r0; \
|
||||
mtmsrd r9,1; /* Clear MSR_RI */ \
|
||||
/* Move original SRR0 and SRR1 into the respective regs */ \
|
||||
ld r9,_MSR(r1); \
|
||||
mtspr SPRN_SRR1,r9; \
|
||||
ld r3,_NIP(r1); \
|
||||
mtspr SPRN_SRR0,r3; \
|
||||
ld r9,_CTR(r1); \
|
||||
mtctr r9; \
|
||||
ld r9,_XER(r1); \
|
||||
mtxer r9; \
|
||||
ld r9,_LINK(r1); \
|
||||
mtlr r9; \
|
||||
REST_GPR(0, r1); \
|
||||
REST_8GPRS(2, r1); \
|
||||
REST_GPR(10, r1); \
|
||||
ld r11,_CCR(r1); \
|
||||
mtcr r11; \
|
||||
/* Decrement paca->in_mce. */ \
|
||||
lhz r12,PACA_IN_MCE(r13); \
|
||||
subi r12,r12,1; \
|
||||
sth r12,PACA_IN_MCE(r13); \
|
||||
REST_GPR(11, r1); \
|
||||
REST_2GPRS(12, r1); \
|
||||
/* restore original r1. */ \
|
||||
ld r1,GPR1(r1)
|
||||
|
||||
/*
|
||||
* Handle machine check early in real mode. We come here with
|
||||
* ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
|
||||
*/
|
||||
EXC_COMMON_BEGIN(machine_check_handle_early)
|
||||
std r0,GPR0(r1) /* Save r0 */
|
||||
EXCEPTION_PROLOG_COMMON_3(0x200)
|
||||
bl save_nvgprs
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
bl machine_check_early
|
||||
std r3,RESULT(r1) /* Save result */
|
||||
ld r12,_MSR(r1)
|
||||
#ifdef CONFIG_PPC_P7_NAP
|
||||
/*
|
||||
* Check if thread was in power saving mode. We come here when any
|
||||
* of the following is true:
|
||||
* a. thread wasn't in power saving mode
|
||||
* b. thread was in power saving mode with no state loss,
|
||||
* supervisor state loss or hypervisor state loss.
|
||||
*
|
||||
* Go back to nap/sleep/winkle mode again if (b) is true.
|
||||
*/
|
||||
rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */
|
||||
beq 4f /* No, it wasn;t */
|
||||
/* Thread was in power saving mode. Go back to nap again. */
|
||||
cmpwi r11,2
|
||||
blt 3f
|
||||
/* Supervisor/Hypervisor state loss */
|
||||
li r0,1
|
||||
stb r0,PACA_NAPSTATELOST(r13)
|
||||
3: bl machine_check_queue_event
|
||||
MACHINE_CHECK_HANDLER_WINDUP
|
||||
GET_PACA(r13)
|
||||
ld r1,PACAR1(r13)
|
||||
/*
|
||||
* Check what idle state this CPU was in and go back to same mode
|
||||
* again.
|
||||
*/
|
||||
lbz r3,PACA_THREAD_IDLE_STATE(r13)
|
||||
cmpwi r3,PNV_THREAD_NAP
|
||||
bgt 10f
|
||||
IDLE_STATE_ENTER_SEQ(PPC_NAP)
|
||||
/* No return */
|
||||
10:
|
||||
cmpwi r3,PNV_THREAD_SLEEP
|
||||
bgt 2f
|
||||
IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
|
||||
/* No return */
|
||||
|
||||
2:
|
||||
/*
|
||||
* Go back to winkle. Please note that this thread was woken up in
|
||||
* machine check from winkle and have not restored the per-subcore
|
||||
* state. Hence before going back to winkle, set last bit of HSPGR0
|
||||
* to 1. This will make sure that if this thread gets woken up
|
||||
* again at reset vector 0x100 then it will get chance to restore
|
||||
* the subcore state.
|
||||
*/
|
||||
ori r13,r13,1
|
||||
SET_PACA(r13)
|
||||
IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
|
||||
/* No return */
|
||||
4:
|
||||
#endif
|
||||
/*
|
||||
* Check if we are coming from hypervisor userspace. If yes then we
|
||||
* continue in host kernel in V mode to deliver the MC event.
|
||||
*/
|
||||
rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */
|
||||
beq 5f
|
||||
andi. r11,r12,MSR_PR /* See if coming from user. */
|
||||
bne 9f /* continue in V mode if we are. */
|
||||
|
||||
5:
|
||||
#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
|
||||
/*
|
||||
* We are coming from kernel context. Check if we are coming from
|
||||
* guest. if yes, then we can continue. We will fall through
|
||||
* do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
|
||||
*/
|
||||
lbz r11,HSTATE_IN_GUEST(r13)
|
||||
cmpwi r11,0 /* Check if coming from guest */
|
||||
bne 9f /* continue if we are. */
|
||||
#endif
|
||||
/*
|
||||
* At this point we are not sure about what context we come from.
|
||||
* Queue up the MCE event and return from the interrupt.
|
||||
* But before that, check if this is an un-recoverable exception.
|
||||
* If yes, then stay on emergency stack and panic.
|
||||
*/
|
||||
andi. r11,r12,MSR_RI
|
||||
bne 2f
|
||||
1: mfspr r11,SPRN_SRR0
|
||||
LOAD_HANDLER(r10,unrecover_mce)
|
||||
mtspr SPRN_SRR0,r10
|
||||
ld r10,PACAKMSR(r13)
|
||||
/*
|
||||
* We are going down. But there are chances that we might get hit by
|
||||
* another MCE during panic path and we may run into unstable state
|
||||
* with no way out. Hence, turn ME bit off while going down, so that
|
||||
* when another MCE is hit during panic path, system will checkstop
|
||||
* and hypervisor will get restarted cleanly by SP.
|
||||
*/
|
||||
li r3,MSR_ME
|
||||
andc r10,r10,r3 /* Turn off MSR_ME */
|
||||
mtspr SPRN_SRR1,r10
|
||||
rfid
|
||||
b .
|
||||
2:
|
||||
/*
|
||||
* Check if we have successfully handled/recovered from error, if not
|
||||
* then stay on emergency stack and panic.
|
||||
*/
|
||||
ld r3,RESULT(r1) /* Load result */
|
||||
cmpdi r3,0 /* see if we handled MCE successfully */
|
||||
|
||||
beq 1b /* if !handled then panic */
|
||||
/*
|
||||
* Return from MC interrupt.
|
||||
* Queue up the MCE event so that we can log it later, while
|
||||
* returning from kernel or opal call.
|
||||
*/
|
||||
bl machine_check_queue_event
|
||||
MACHINE_CHECK_HANDLER_WINDUP
|
||||
rfid
|
||||
9:
|
||||
/* Deliver the machine check to host kernel in V mode. */
|
||||
MACHINE_CHECK_HANDLER_WINDUP
|
||||
b machine_check_pSeries
|
||||
|
||||
EXC_COMMON_BEGIN(unrecover_mce)
|
||||
/* Invoke machine_check_exception to print MCE event and panic. */
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
bl machine_check_exception
|
||||
/*
|
||||
* We will not reach here. Even if we did, there is no way out. Call
|
||||
* unrecoverable_exception and die.
|
||||
*/
|
||||
1: addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
bl unrecoverable_exception
|
||||
b 1b
|
||||
|
||||
/*
|
||||
* r13 points to the PACA, r9 contains the saved CR,
|
||||
* r12 contain the saved SRR1, SRR0 is still ready for return
|
||||
|
|
|
|||
Loading…
Reference in New Issue