MIPS: CM: Specify register size when generating accessors
Some CM registers are always 32 bits, or at least only use bits in the lower 32 bits of the register. For these registers it is wasteful for us to generate accessors which bother to check mips_cm_is64 & perform 64 bit accesses. This patch modifies the accessor generation to take into account the size of the register, and for 32 bit registers we generate accessors which only ever perform 32 bit accesses. For 64 bit registers we either perform a 64 bit access or two 32 bit accesses, depending upon the value of mips_cm_is64. Doing this saves us ~1.5KiB of code in a generic 64r6el kernel, and perhaps more importantly simplifies various code paths. This removes the read64_gcr_* accessors, so mips_cm_error_report() is modified to stop using them & instead use the regular read_gcr_* accessors which will return 64 bit values from the 64 bit registers. The new accessor macros are placed in asm/mips-cps.h such that they can be shared by CPC & GIC code in later patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17000/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>hifive-unleashed-5.1
Paul Burton
Ralf Baechle
parent
abe852ea3a
commit
b025d51873
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@ -15,6 +15,7 @@
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/types.h>
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#include <asm/mips-cps.h>
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/* The base address of the CM GCR block */
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extern void __iomem *mips_gcr_base;
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@ -112,122 +113,57 @@ static inline bool mips_cm_has_l2sync(void)
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/* Size of the L2-only sync region */
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#define MIPS_CM_L2SYNC_SIZE 0x1000
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/* Macros to ease the creation of register access functions */
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#define BUILD_CM_R_(name, off) \
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static inline unsigned long __iomem *addr_gcr_##name(void) \
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{ \
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return (unsigned long __iomem *)(mips_gcr_base + (off));\
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} \
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\
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static inline u32 read32_gcr_##name(void) \
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{ \
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return __raw_readl(addr_gcr_##name()); \
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} \
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\
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static inline u64 read64_gcr_##name(void) \
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{ \
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void __iomem *addr = addr_gcr_##name(); \
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u64 ret; \
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\
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if (mips_cm_is64) { \
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ret = __raw_readq(addr); \
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} else { \
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ret = __raw_readl(addr); \
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ret |= (u64)__raw_readl(addr + 0x4) << 32; \
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} \
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\
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return ret; \
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} \
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\
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static inline unsigned long read_gcr_##name(void) \
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{ \
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if (mips_cm_is64) \
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return read64_gcr_##name(); \
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else \
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return read32_gcr_##name(); \
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}
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#define GCR_ACCESSOR_RO(sz, off, name) \
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CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_GCB_OFS + off, name)
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#define BUILD_CM__W(name, off) \
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static inline void write32_gcr_##name(u32 value) \
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{ \
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__raw_writel(value, addr_gcr_##name()); \
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} \
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\
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static inline void write64_gcr_##name(u64 value) \
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{ \
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__raw_writeq(value, addr_gcr_##name()); \
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} \
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\
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static inline void write_gcr_##name(unsigned long value) \
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{ \
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if (mips_cm_is64) \
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write64_gcr_##name(value); \
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else \
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write32_gcr_##name(value); \
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}
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#define GCR_ACCESSOR_RW(sz, off, name) \
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CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_GCB_OFS + off, name)
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#define BUILD_CM_RW(name, off) \
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BUILD_CM_R_(name, off) \
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BUILD_CM__W(name, off)
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#define GCR_CX_ACCESSOR_RO(sz, off, name) \
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CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \
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CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
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#define BUILD_CM_Cx_R_(name, off) \
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BUILD_CM_R_(cl_##name, MIPS_CM_CLCB_OFS + (off)) \
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BUILD_CM_R_(co_##name, MIPS_CM_COCB_OFS + (off))
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#define BUILD_CM_Cx__W(name, off) \
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BUILD_CM__W(cl_##name, MIPS_CM_CLCB_OFS + (off)) \
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BUILD_CM__W(co_##name, MIPS_CM_COCB_OFS + (off))
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#define BUILD_CM_Cx_RW(name, off) \
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BUILD_CM_Cx_R_(name, off) \
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BUILD_CM_Cx__W(name, off)
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#define GCR_CX_ACCESSOR_RW(sz, off, name) \
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CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \
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CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
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/* GCB register accessor functions */
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BUILD_CM_R_(config, MIPS_CM_GCB_OFS + 0x00)
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BUILD_CM_RW(base, MIPS_CM_GCB_OFS + 0x08)
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BUILD_CM_RW(access, MIPS_CM_GCB_OFS + 0x20)
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BUILD_CM_R_(rev, MIPS_CM_GCB_OFS + 0x30)
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BUILD_CM_RW(err_control, MIPS_CM_GCB_OFS + 0x38)
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BUILD_CM_RW(error_mask, MIPS_CM_GCB_OFS + 0x40)
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BUILD_CM_RW(error_cause, MIPS_CM_GCB_OFS + 0x48)
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BUILD_CM_RW(error_addr, MIPS_CM_GCB_OFS + 0x50)
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BUILD_CM_RW(error_mult, MIPS_CM_GCB_OFS + 0x58)
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BUILD_CM_RW(l2_only_sync_base, MIPS_CM_GCB_OFS + 0x70)
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BUILD_CM_RW(gic_base, MIPS_CM_GCB_OFS + 0x80)
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BUILD_CM_RW(cpc_base, MIPS_CM_GCB_OFS + 0x88)
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BUILD_CM_RW(reg0_base, MIPS_CM_GCB_OFS + 0x90)
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BUILD_CM_RW(reg0_mask, MIPS_CM_GCB_OFS + 0x98)
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BUILD_CM_RW(reg1_base, MIPS_CM_GCB_OFS + 0xa0)
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BUILD_CM_RW(reg1_mask, MIPS_CM_GCB_OFS + 0xa8)
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BUILD_CM_RW(reg2_base, MIPS_CM_GCB_OFS + 0xb0)
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BUILD_CM_RW(reg2_mask, MIPS_CM_GCB_OFS + 0xb8)
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BUILD_CM_RW(reg3_base, MIPS_CM_GCB_OFS + 0xc0)
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BUILD_CM_RW(reg3_mask, MIPS_CM_GCB_OFS + 0xc8)
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BUILD_CM_R_(gic_status, MIPS_CM_GCB_OFS + 0xd0)
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BUILD_CM_R_(cpc_status, MIPS_CM_GCB_OFS + 0xf0)
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BUILD_CM_RW(l2_config, MIPS_CM_GCB_OFS + 0x130)
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BUILD_CM_RW(sys_config2, MIPS_CM_GCB_OFS + 0x150)
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BUILD_CM_RW(l2_pft_control, MIPS_CM_GCB_OFS + 0x300)
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BUILD_CM_RW(l2_pft_control_b, MIPS_CM_GCB_OFS + 0x308)
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BUILD_CM_RW(bev_base, MIPS_CM_GCB_OFS + 0x680)
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GCR_ACCESSOR_RO(64, 0x000, config)
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GCR_ACCESSOR_RW(64, 0x008, base)
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GCR_ACCESSOR_RW(32, 0x020, access)
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GCR_ACCESSOR_RO(32, 0x030, rev)
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GCR_ACCESSOR_RW(32, 0x038, err_control)
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GCR_ACCESSOR_RW(64, 0x040, error_mask)
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GCR_ACCESSOR_RW(64, 0x048, error_cause)
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GCR_ACCESSOR_RW(64, 0x050, error_addr)
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GCR_ACCESSOR_RW(64, 0x058, error_mult)
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GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
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GCR_ACCESSOR_RW(64, 0x080, gic_base)
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GCR_ACCESSOR_RW(64, 0x088, cpc_base)
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GCR_ACCESSOR_RW(64, 0x090, reg0_base)
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GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
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GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
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GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
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GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
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GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
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GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
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GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
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GCR_ACCESSOR_RO(32, 0x0d0, gic_status)
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GCR_ACCESSOR_RO(32, 0x0f0, cpc_status)
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GCR_ACCESSOR_RW(32, 0x130, l2_config)
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GCR_ACCESSOR_RO(32, 0x150, sys_config2)
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GCR_ACCESSOR_RW(32, 0x300, l2_pft_control)
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GCR_ACCESSOR_RW(32, 0x308, l2_pft_control_b)
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GCR_ACCESSOR_RW(64, 0x680, bev_base)
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/* Core Local & Core Other register accessor functions */
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BUILD_CM_Cx_RW(reset_release, 0x00)
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BUILD_CM_Cx_RW(coherence, 0x08)
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BUILD_CM_Cx_R_(config, 0x10)
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BUILD_CM_Cx_RW(other, 0x18)
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BUILD_CM_Cx_RW(reset_base, 0x20)
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BUILD_CM_Cx_R_(id, 0x28)
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BUILD_CM_Cx_RW(reset_ext_base, 0x30)
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BUILD_CM_Cx_R_(tcid_0_priority, 0x40)
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BUILD_CM_Cx_R_(tcid_1_priority, 0x48)
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BUILD_CM_Cx_R_(tcid_2_priority, 0x50)
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BUILD_CM_Cx_R_(tcid_3_priority, 0x58)
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BUILD_CM_Cx_R_(tcid_4_priority, 0x60)
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BUILD_CM_Cx_R_(tcid_5_priority, 0x68)
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BUILD_CM_Cx_R_(tcid_6_priority, 0x70)
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BUILD_CM_Cx_R_(tcid_7_priority, 0x78)
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BUILD_CM_Cx_R_(tcid_8_priority, 0x80)
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GCR_CX_ACCESSOR_RW(32, 0x000, reset_release)
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GCR_CX_ACCESSOR_RW(32, 0x008, coherence)
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GCR_CX_ACCESSOR_RO(32, 0x010, config)
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GCR_CX_ACCESSOR_RW(32, 0x018, other)
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GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
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GCR_CX_ACCESSOR_RO(32, 0x028, id)
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GCR_CX_ACCESSOR_RW(32, 0x030, reset_ext_base)
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/* GCR_CONFIG register fields */
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#define CM_GCR_CONFIG_NUMIOCU_SHF 8
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@ -0,0 +1,87 @@
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/*
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* Copyright (C) 2017 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __MIPS_ASM_MIPS_CPS_H__
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#define __MIPS_ASM_MIPS_CPS_H__
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#include <linux/io.h>
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#include <linux/types.h>
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extern unsigned long __cps_access_bad_size(void)
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__compiletime_error("Bad size for CPS accessor");
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#define CPS_ACCESSOR_A(unit, off, name) \
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static inline void *addr_##unit##_##name(void) \
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{ \
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return mips_##unit##_base + (off); \
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}
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#define CPS_ACCESSOR_R(unit, sz, name) \
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static inline uint##sz##_t read_##unit##_##name(void) \
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{ \
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uint64_t val64; \
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\
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switch (sz) { \
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case 32: \
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return __raw_readl(addr_##unit##_##name()); \
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\
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case 64: \
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if (mips_cm_is64) \
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return __raw_readq(addr_##unit##_##name()); \
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\
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val64 = __raw_readl(addr_##unit##_##name() + 4); \
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val64 <<= 32; \
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val64 |= __raw_readl(addr_##unit##_##name()); \
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return val64; \
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\
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default: \
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return __cps_access_bad_size(); \
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} \
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}
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#define CPS_ACCESSOR_W(unit, sz, name) \
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static inline void write_##unit##_##name(uint##sz##_t val) \
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{ \
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switch (sz) { \
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case 32: \
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__raw_writel(val, addr_##unit##_##name()); \
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break; \
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\
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case 64: \
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if (mips_cm_is64) { \
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__raw_writeq(val, addr_##unit##_##name()); \
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break; \
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} \
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\
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__raw_writel((uint64_t)val >> 32, \
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addr_##unit##_##name() + 4); \
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__raw_writel(val, addr_##unit##_##name()); \
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break; \
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\
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default: \
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__cps_access_bad_size(); \
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break; \
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} \
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}
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#define CPS_ACCESSOR_RO(unit, sz, off, name) \
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CPS_ACCESSOR_A(unit, off, name) \
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CPS_ACCESSOR_R(unit, sz, name)
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#define CPS_ACCESSOR_WO(unit, sz, off, name) \
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CPS_ACCESSOR_A(unit, off, name) \
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CPS_ACCESSOR_W(unit, sz, name)
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#define CPS_ACCESSOR_RW(unit, sz, off, name) \
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CPS_ACCESSOR_A(unit, off, name) \
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CPS_ACCESSOR_R(unit, sz, name) \
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CPS_ACCESSOR_W(unit, sz, name)
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#endif /* __MIPS_ASM_MIPS_CPS_H__ */
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@ -332,11 +332,11 @@ void mips_cm_error_report(void)
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return;
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revision = mips_cm_revision();
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cm_error = read_gcr_error_cause();
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cm_addr = read_gcr_error_addr();
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cm_other = read_gcr_error_mult();
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if (revision < CM_REV_CM3) { /* CM2 */
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cm_error = read_gcr_error_cause();
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cm_addr = read_gcr_error_addr();
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cm_other = read_gcr_error_mult();
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cause = cm_error >> CM_GCR_ERROR_CAUSE_ERRTYPE_SHF;
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ocause = cm_other >> CM_GCR_ERROR_MULT_ERR2ND_SHF;
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@ -380,9 +380,6 @@ void mips_cm_error_report(void)
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ulong core_id_bits, vp_id_bits, cmd_bits, cmd_group_bits;
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ulong cm3_cca_bits, mcp_bits, cm3_tr_bits, sched_bit;
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cm_error = read64_gcr_error_cause();
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cm_addr = read64_gcr_error_addr();
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cm_other = read64_gcr_error_mult();
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cause = cm_error >> CM3_GCR_ERROR_CAUSE_ERRTYPE_SHF;
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ocause = cm_other >> CM_GCR_ERROR_MULT_ERR2ND_SHF;
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