drm: radeon: Fix ring_rptr accesses.
The memory behind ring_rptr can either be in ioremapped memory or a vmalloc() normal kernel memory buffer. However, the code unconditionally uses DRM_{READ,WRITE}32() (and thus readl() and writel()) to access it. Basically, if RADEON_IS_AGP then it's ioremap()'d memory else it's vmalloc'd memory. Adjust all of the ring_rptr access code as needed. While we're here, kill the 'scratch' pointer in drm_radeon_private. It's only used in the one place where it is initialized. Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Dave Airlie <airlied@linux.ie>
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@ -43,6 +43,52 @@
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static int radeon_do_cleanup_cp(struct drm_device * dev);
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static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
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static u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
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{
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u32 val;
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if (dev_priv->flags & RADEON_IS_AGP) {
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val = DRM_READ32(dev_priv->ring_rptr, off);
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} else {
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val = *(((volatile u32 *)
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dev_priv->ring_rptr->handle) +
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(off / sizeof(u32)));
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val = le32_to_cpu(val);
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}
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return val;
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}
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u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
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{
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if (dev_priv->writeback_works)
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return radeon_read_ring_rptr(dev_priv, 0);
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else
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return RADEON_READ(RADEON_CP_RB_RPTR);
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}
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static void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
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{
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if (dev_priv->flags & RADEON_IS_AGP)
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DRM_WRITE32(dev_priv->ring_rptr, off, val);
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else
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*(((volatile u32 *) dev_priv->ring_rptr->handle) +
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(off / sizeof(u32))) = cpu_to_le32(val);
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}
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void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
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{
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radeon_write_ring_rptr(dev_priv, 0, val);
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}
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u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
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{
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if (dev_priv->writeback_works)
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return radeon_read_ring_rptr(dev_priv,
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RADEON_SCRATCHOFF(index));
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else
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return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
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}
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static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
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{
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u32 ret;
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@ -649,10 +695,6 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
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RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
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+ RADEON_SCRATCH_REG_OFFSET);
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dev_priv->scratch = ((__volatile__ u32 *)
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dev_priv->ring_rptr->handle +
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(RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
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RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
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/* Turn on bus mastering */
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@ -670,13 +712,13 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
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RADEON_WRITE(RADEON_BUS_CNTL, tmp);
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} /* PCIE cards appears to not need this */
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dev_priv->scratch[0] = 0;
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radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
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RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
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dev_priv->scratch[1] = 0;
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radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
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RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
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dev_priv->scratch[2] = 0;
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radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
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RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
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/* reset sarea copies of these */
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@ -708,12 +750,15 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
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/* Writeback doesn't seem to work everywhere, test it here and possibly
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* enable it if it appears to work
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*/
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DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
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radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
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RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
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for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
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if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
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0xdeadbeef)
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u32 val;
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val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
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if (val == 0xdeadbeef)
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break;
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DRM_UDELAY(1);
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}
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@ -1549,7 +1594,7 @@ struct drm_buf *radeon_freelist_get(struct drm_device * dev)
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start = dev_priv->last_buf;
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for (t = 0; t < dev_priv->usec_timeout; t++) {
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u32 done_age = GET_SCRATCH(1);
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u32 done_age = GET_SCRATCH(dev_priv, 1);
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DRM_DEBUG("done_age = %d\n", done_age);
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for (i = start; i < dma->buf_count; i++) {
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buf = dma->buflist[i];
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@ -1583,8 +1628,9 @@ struct drm_buf *radeon_freelist_get(struct drm_device * dev)
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struct drm_buf *buf;
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int i, t;
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int start;
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u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
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u32 done_age;
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done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
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if (++dev_priv->last_buf >= dma->buf_count)
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dev_priv->last_buf = 0;
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@ -160,10 +160,6 @@ enum radeon_chip_flags {
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RADEON_IS_IGPGART = 0x01000000UL,
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};
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#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
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DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
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#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
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typedef struct drm_radeon_freelist {
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unsigned int age;
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struct drm_buf *buf;
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@ -248,7 +244,6 @@ typedef struct drm_radeon_private {
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drm_radeon_freelist_t *head;
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drm_radeon_freelist_t *tail;
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int last_buf;
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volatile u32 *scratch;
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int writeback_works;
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int usec_timeout;
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@ -338,6 +333,12 @@ extern int radeon_no_wb;
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extern struct drm_ioctl_desc radeon_ioctls[];
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extern int radeon_max_ioctl;
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extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv);
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extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val);
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#define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv)
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#define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val)
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/* Check whether the given hardware address is inside the framebuffer or the
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* GART area.
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*/
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@ -639,9 +640,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
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#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
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#define GET_SCRATCH( x ) (dev_priv->writeback_works \
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? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
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: RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
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extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
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#define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x)
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#define RADEON_GEN_INT_CNTL 0x0040
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# define RADEON_CRTC_VBLANK_MASK (1 << 0)
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@ -3010,14 +3010,14 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
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break;
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case RADEON_PARAM_LAST_FRAME:
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dev_priv->stats.last_frame_reads++;
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value = GET_SCRATCH(0);
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value = GET_SCRATCH(dev_priv, 0);
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break;
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case RADEON_PARAM_LAST_DISPATCH:
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value = GET_SCRATCH(1);
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value = GET_SCRATCH(dev_priv, 1);
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break;
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case RADEON_PARAM_LAST_CLEAR:
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dev_priv->stats.last_clear_reads++;
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value = GET_SCRATCH(2);
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value = GET_SCRATCH(dev_priv, 2);
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break;
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case RADEON_PARAM_IRQ_NR:
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value = drm_dev_to_irq(dev);
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