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ASoC: SOF: Intel: hda: add SSP info to the chip info struct

add SSP info of APL and CNL, to the sof_intel_dsp_desc
structure. The max SSP count the platform support and
the SSP base address.

Signed-off-by: Zhu Yingjiang <yingjiang.zhu@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
hifive-unleashed-5.2
Zhu Yingjiang 2019-04-30 18:09:21 -05:00 committed by Mark Brown
parent df7e0de588
commit b095fe47bc
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
4 changed files with 10 additions and 0 deletions

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@ -105,5 +105,7 @@ const struct sof_intel_dsp_desc apl_chip_info = {
.ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
.ipc_ctl = HDA_DSP_REG_HIPCCTL,
.rom_init_timeout = 150,
.ssp_count = APL_SSP_COUNT,
.ssp_base_offset = APL_SSP_BASE_OFFSET,
};
EXPORT_SYMBOL(apl_chip_info);

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@ -246,5 +246,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
.ipc_ctl = CNL_DSP_REG_HIPCCTL,
.rom_init_timeout = 300,
.ssp_count = CNL_SSP_COUNT,
.ssp_base_offset = CNL_SSP_BASE_OFFSET,
};
EXPORT_SYMBOL(cnl_chip_info);

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@ -345,6 +345,10 @@
/* Host Device Memory Size of a Single SSP */
#define SSP_DEV_MEM_SIZE 0x1000
/* SSP Count of the Platform */
#define APL_SSP_COUNT 6
#define CNL_SSP_COUNT 3
#define HDA_IDISP_CODEC(x) ((x) & BIT(2))
struct sof_intel_dsp_bdl {

View File

@ -162,6 +162,8 @@ struct sof_intel_dsp_desc {
int ipc_ack_mask;
int ipc_ctl;
int rom_init_timeout;
int ssp_count; /* ssp count of the platform */
int ssp_base_offset; /* base address of the SSPs */
};
extern const struct snd_sof_dsp_ops sof_tng_ops;