i.MX drivers change for 4.20, round 2:
- A series from Aisheng Dong to add SCU firmware driver for i.MX8
SoCs. It implements IPC mechanism based on mailbox for message
exchange between AP and SCU firmware, and a set of SCU IPC
service APIs used by clients like i.MX8 power domain and clock
drivers.
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Merge tag 'imx-drivers-4.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/drivers
i.MX drivers change for 4.20, round 2:
- A series from Aisheng Dong to add SCU firmware driver for i.MX8
SoCs. It implements IPC mechanism based on mailbox for message
exchange between AP and SCU firmware, and a set of SCU IPC
service APIs used by clients like i.MX8 power domain and clock
drivers.
* tag 'imx-drivers-4.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
MAINTAINERS: imx: include drivers/firmware/imx path
firmware: imx: add misc svc support
firmware: imx: add SCU firmware driver support
dt-bindings: arm: fsl: add scu binding doc
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
hifive-unleashed-5.1
Arnd Bergmann
commit
b0a2cea5eb
|
|
@ -0,0 +1,183 @@
|
|||
NXP i.MX System Controller Firmware (SCFW)
|
||||
--------------------------------------------------------------------
|
||||
|
||||
The System Controller Firmware (SCFW) is a low-level system function
|
||||
which runs on a dedicated Cortex-M core to provide power, clock, and
|
||||
resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
|
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(QM, QP), and i.MX8QX (QXP, DX).
|
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|
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The AP communicates with the SC using a multi-ported MU module found
|
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in the LSIO subsystem. The current definition of this MU module provides
|
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5 remote AP connections to the SC to support up to 5 execution environments
|
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(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
|
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with the LSIO DSC IP bus. The SC firmware will communicate with this MU
|
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using the MSI bus.
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|
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System Controller Device Node:
|
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============================================================
|
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The scu node with the following properties shall be under the /firmware/ node.
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|
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Required properties:
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-------------------
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- compatible: should be "fsl,imx-scu".
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- mbox-names: should include "tx0", "tx1", "tx2", "tx3",
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"rx0", "rx1", "rx2", "rx3".
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- mboxes: List of phandle of 4 MU channels for tx and 4 MU channels
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for rx. All 8 MU channels must be in the same MU instance.
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Cross instances are not allowed. The MU instance can only
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be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
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to make sure use the one which is not conflict with other
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execution environments. e.g. ATF.
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Note:
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Channel 0 must be "tx0" or "rx0".
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Channel 1 must be "tx1" or "rx1".
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Channel 2 must be "tx2" or "rx2".
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Channel 3 must be "tx3" or "rx3".
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e.g.
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mboxes = <&lsio_mu1 0 0
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&lsio_mu1 0 1
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&lsio_mu1 0 2
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&lsio_mu1 0 3
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&lsio_mu1 1 0
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&lsio_mu1 1 1
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&lsio_mu1 1 2
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&lsio_mu1 1 3>;
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See Documentation/devicetree/bindings/mailbox/fsl,mu.txt
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for detailed mailbox binding.
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i.MX SCU Client Device Node:
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============================================================
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Client nodes are maintained as children of the relevant IMX-SCU device node.
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Power domain bindings based on SCU Message Protocol
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------------------------------------------------------------
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This binding for the SCU power domain providers uses the generic power
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domain binding[2].
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Required properties:
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- compatible: Should be "fsl,scu-pd".
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- #address-cells: Should be 1.
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- #size-cells: Should be 0.
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|
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Required properties for power domain sub nodes:
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- #power-domain-cells: Must be 0.
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Optional Properties:
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- reg: Resource ID of this power domain.
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No exist means uncontrollable by user.
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See detailed Resource ID list from:
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include/dt-bindings/power/imx-rsrc.h
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- power-domains: phandle pointing to the parent power domain.
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Clock bindings based on SCU Message Protocol
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------------------------------------------------------------
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This binding uses the common clock binding[1].
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Required properties:
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- compatible: Should be "fsl,imx8qxp-clock".
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- #clock-cells: Should be 1. Contains the Clock ID value.
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- clocks: List of clock specifiers, must contain an entry for
|
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each required entry in clock-names
|
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- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"
|
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|
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell.
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|
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See the full list of clock IDs from:
|
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include/dt-bindings/clock/imx8qxp-clock.h
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Pinctrl bindings based on SCU Message Protocol
|
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------------------------------------------------------------
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This binding uses the i.MX common pinctrl binding[3].
|
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|
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Required properties:
|
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- compatible: Should be "fsl,imx8qxp-iomuxc".
|
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|
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Required properties for Pinctrl sub nodes:
|
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- fsl,pins: Each entry consists of 3 integers which represents
|
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the mux and config setting for one pin. The first 2
|
||||
integers <pin_id mux_mode> are specified using a
|
||||
PIN_FUNC_ID macro, which can be found in
|
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<dt-bindings/pinctrl/pads-imx8qxp.h>.
|
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The last integer CONFIG is the pad setting value like
|
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pull-up on this pin.
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|
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Please refer to i.MX8QXP Reference Manual for detailed
|
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CONFIG settings.
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/power/power_domain.txt
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[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
|
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|
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Example (imx8qxp):
|
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-------------
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lsio_mu1: mailbox@5d1c0000 {
|
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...
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#mbox-cells = <2>;
|
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};
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|
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firmware {
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scu {
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compatible = "fsl,imx-scu";
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mbox-names = "tx0", "tx1", "tx2", "tx3",
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"rx0", "rx1", "rx2", "rx3";
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mboxes = <&lsio_mu1 0 0
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&lsio_mu1 0 1
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&lsio_mu1 0 2
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&lsio_mu1 0 3
|
||||
&lsio_mu1 1 0
|
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&lsio_mu1 1 1
|
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&lsio_mu1 1 2
|
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&lsio_mu1 1 3>;
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|
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clk: clk {
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compatible = "fsl,imx8qxp-clk";
|
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#clock-cells = <1>;
|
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};
|
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iomuxc {
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compatible = "fsl,imx8qxp-iomuxc";
|
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|
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pinctrl_lpuart0: lpuart0grp {
|
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fsl,pins = <
|
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SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
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SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
|
||||
>;
|
||||
};
|
||||
...
|
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};
|
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|
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imx8qx-pm {
|
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compatible = "fsl,scu-pd";
|
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#address-cells = <1>;
|
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#size-cells = <0>;
|
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|
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pd_dma: dma-power-domain {
|
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#power-domain-cells = <0>;
|
||||
|
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pd_dma_lpuart0: dma-lpuart0@57 {
|
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reg = <SC_R_UART_0>;
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&pd_dma>;
|
||||
};
|
||||
...
|
||||
};
|
||||
...
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial@5a060000 {
|
||||
...
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart0>;
|
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clocks = <&clk IMX8QXP_UART0_CLK>,
|
||||
<&clk IMX8QXP_UART0_IPG_CLK>;
|
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clock-names = "per", "ipg";
|
||||
power-domains = <&pd_dma_lpuart0>;
|
||||
};
|
||||
|
|
@ -1462,7 +1462,9 @@ F: arch/arm/mach-mxs/
|
|||
F: arch/arm/boot/dts/imx*
|
||||
F: arch/arm/configs/imx*_defconfig
|
||||
F: drivers/clk/imx/
|
||||
F: drivers/firmware/imx/
|
||||
F: drivers/soc/imx/
|
||||
F: include/linux/firmware/imx/
|
||||
F: include/soc/imx/
|
||||
|
||||
ARM/FREESCALE VYBRID ARM ARCHITECTURE
|
||||
|
|
|
|||
|
|
@ -289,6 +289,7 @@ config HAVE_ARM_SMCCC
|
|||
source "drivers/firmware/broadcom/Kconfig"
|
||||
source "drivers/firmware/google/Kconfig"
|
||||
source "drivers/firmware/efi/Kconfig"
|
||||
source "drivers/firmware/imx/Kconfig"
|
||||
source "drivers/firmware/meson/Kconfig"
|
||||
source "drivers/firmware/tegra/Kconfig"
|
||||
source "drivers/firmware/xilinx/Kconfig"
|
||||
|
|
|
|||
|
|
@ -31,5 +31,6 @@ obj-y += meson/
|
|||
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
|
||||
obj-$(CONFIG_EFI) += efi/
|
||||
obj-$(CONFIG_UEFI_CPER) += efi/
|
||||
obj-y += imx/
|
||||
obj-y += tegra/
|
||||
obj-y += xilinx/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,11 @@
|
|||
config IMX_SCU
|
||||
bool "IMX SCU Protocol driver"
|
||||
depends on IMX_MBOX
|
||||
help
|
||||
The System Controller Firmware (SCFW) is a low-level system function
|
||||
which runs on a dedicated Cortex-M core to provide power, clock, and
|
||||
resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
|
||||
(QM, QP), and i.MX8QX (QXP, DX).
|
||||
|
||||
This driver manages the IPC interface between host CPU and the
|
||||
SCU firmware running on M4.
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o
|
||||
|
|
@ -0,0 +1,270 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
* Author: Dong Aisheng <aisheng.dong@nxp.com>
|
||||
*
|
||||
* Implementation of the SCU IPC functions using MUs (client side).
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/firmware/imx/types.h>
|
||||
#include <linux/firmware/imx/ipc.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mailbox_client.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#define SCU_MU_CHAN_NUM 8
|
||||
#define MAX_RX_TIMEOUT (msecs_to_jiffies(30))
|
||||
|
||||
struct imx_sc_chan {
|
||||
struct imx_sc_ipc *sc_ipc;
|
||||
|
||||
struct mbox_client cl;
|
||||
struct mbox_chan *ch;
|
||||
int idx;
|
||||
};
|
||||
|
||||
struct imx_sc_ipc {
|
||||
/* SCU uses 4 Tx and 4 Rx channels */
|
||||
struct imx_sc_chan chans[SCU_MU_CHAN_NUM];
|
||||
struct device *dev;
|
||||
struct mutex lock;
|
||||
struct completion done;
|
||||
|
||||
/* temporarily store the SCU msg */
|
||||
u32 *msg;
|
||||
u8 rx_size;
|
||||
u8 count;
|
||||
};
|
||||
|
||||
/*
|
||||
* This type is used to indicate error response for most functions.
|
||||
*/
|
||||
enum imx_sc_error_codes {
|
||||
IMX_SC_ERR_NONE = 0, /* Success */
|
||||
IMX_SC_ERR_VERSION = 1, /* Incompatible API version */
|
||||
IMX_SC_ERR_CONFIG = 2, /* Configuration error */
|
||||
IMX_SC_ERR_PARM = 3, /* Bad parameter */
|
||||
IMX_SC_ERR_NOACCESS = 4, /* Permission error (no access) */
|
||||
IMX_SC_ERR_LOCKED = 5, /* Permission error (locked) */
|
||||
IMX_SC_ERR_UNAVAILABLE = 6, /* Unavailable (out of resources) */
|
||||
IMX_SC_ERR_NOTFOUND = 7, /* Not found */
|
||||
IMX_SC_ERR_NOPOWER = 8, /* No power */
|
||||
IMX_SC_ERR_IPC = 9, /* Generic IPC error */
|
||||
IMX_SC_ERR_BUSY = 10, /* Resource is currently busy/active */
|
||||
IMX_SC_ERR_FAIL = 11, /* General I/O failure */
|
||||
IMX_SC_ERR_LAST
|
||||
};
|
||||
|
||||
static int imx_sc_linux_errmap[IMX_SC_ERR_LAST] = {
|
||||
0, /* IMX_SC_ERR_NONE */
|
||||
-EINVAL, /* IMX_SC_ERR_VERSION */
|
||||
-EINVAL, /* IMX_SC_ERR_CONFIG */
|
||||
-EINVAL, /* IMX_SC_ERR_PARM */
|
||||
-EACCES, /* IMX_SC_ERR_NOACCESS */
|
||||
-EACCES, /* IMX_SC_ERR_LOCKED */
|
||||
-ERANGE, /* IMX_SC_ERR_UNAVAILABLE */
|
||||
-EEXIST, /* IMX_SC_ERR_NOTFOUND */
|
||||
-EPERM, /* IMX_SC_ERR_NOPOWER */
|
||||
-EPIPE, /* IMX_SC_ERR_IPC */
|
||||
-EBUSY, /* IMX_SC_ERR_BUSY */
|
||||
-EIO, /* IMX_SC_ERR_FAIL */
|
||||
};
|
||||
|
||||
static struct imx_sc_ipc *imx_sc_ipc_handle;
|
||||
|
||||
static inline int imx_sc_to_linux_errno(int errno)
|
||||
{
|
||||
if (errno >= IMX_SC_ERR_NONE && errno < IMX_SC_ERR_LAST)
|
||||
return imx_sc_linux_errmap[errno];
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the default handle used by SCU
|
||||
*/
|
||||
int imx_scu_get_handle(struct imx_sc_ipc **ipc)
|
||||
{
|
||||
if (!imx_sc_ipc_handle)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
*ipc = imx_sc_ipc_handle;
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(imx_scu_get_handle);
|
||||
|
||||
static void imx_scu_rx_callback(struct mbox_client *c, void *msg)
|
||||
{
|
||||
struct imx_sc_chan *sc_chan = container_of(c, struct imx_sc_chan, cl);
|
||||
struct imx_sc_ipc *sc_ipc = sc_chan->sc_ipc;
|
||||
struct imx_sc_rpc_msg *hdr;
|
||||
u32 *data = msg;
|
||||
|
||||
if (sc_chan->idx == 0) {
|
||||
hdr = msg;
|
||||
sc_ipc->rx_size = hdr->size;
|
||||
dev_dbg(sc_ipc->dev, "msg rx size %u\n", sc_ipc->rx_size);
|
||||
if (sc_ipc->rx_size > 4)
|
||||
dev_warn(sc_ipc->dev, "RPC does not support receiving over 4 words: %u\n",
|
||||
sc_ipc->rx_size);
|
||||
}
|
||||
|
||||
sc_ipc->msg[sc_chan->idx] = *data;
|
||||
sc_ipc->count++;
|
||||
|
||||
dev_dbg(sc_ipc->dev, "mu %u msg %u 0x%x\n", sc_chan->idx,
|
||||
sc_ipc->count, *data);
|
||||
|
||||
if ((sc_ipc->rx_size != 0) && (sc_ipc->count == sc_ipc->rx_size))
|
||||
complete(&sc_ipc->done);
|
||||
}
|
||||
|
||||
static int imx_scu_ipc_write(struct imx_sc_ipc *sc_ipc, void *msg)
|
||||
{
|
||||
struct imx_sc_rpc_msg *hdr = msg;
|
||||
struct imx_sc_chan *sc_chan;
|
||||
u32 *data = msg;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
/* Check size */
|
||||
if (hdr->size > IMX_SC_RPC_MAX_MSG)
|
||||
return -EINVAL;
|
||||
|
||||
dev_dbg(sc_ipc->dev, "RPC SVC %u FUNC %u SIZE %u\n", hdr->svc,
|
||||
hdr->func, hdr->size);
|
||||
|
||||
for (i = 0; i < hdr->size; i++) {
|
||||
sc_chan = &sc_ipc->chans[i % 4];
|
||||
ret = mbox_send_message(sc_chan->ch, &data[i]);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* RPC command/response
|
||||
*/
|
||||
int imx_scu_call_rpc(struct imx_sc_ipc *sc_ipc, void *msg, bool have_resp)
|
||||
{
|
||||
struct imx_sc_rpc_msg *hdr;
|
||||
int ret;
|
||||
|
||||
if (WARN_ON(!sc_ipc || !msg))
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&sc_ipc->lock);
|
||||
reinit_completion(&sc_ipc->done);
|
||||
|
||||
sc_ipc->msg = msg;
|
||||
sc_ipc->count = 0;
|
||||
ret = imx_scu_ipc_write(sc_ipc, msg);
|
||||
if (ret < 0) {
|
||||
dev_err(sc_ipc->dev, "RPC send msg failed: %d\n", ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (have_resp) {
|
||||
if (!wait_for_completion_timeout(&sc_ipc->done,
|
||||
MAX_RX_TIMEOUT)) {
|
||||
dev_err(sc_ipc->dev, "RPC send msg timeout\n");
|
||||
mutex_unlock(&sc_ipc->lock);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
/* response status is stored in hdr->func field */
|
||||
hdr = msg;
|
||||
ret = hdr->func;
|
||||
}
|
||||
|
||||
out:
|
||||
mutex_unlock(&sc_ipc->lock);
|
||||
|
||||
dev_dbg(sc_ipc->dev, "RPC SVC done\n");
|
||||
|
||||
return imx_sc_to_linux_errno(ret);
|
||||
}
|
||||
EXPORT_SYMBOL(imx_scu_call_rpc);
|
||||
|
||||
static int imx_scu_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct imx_sc_ipc *sc_ipc;
|
||||
struct imx_sc_chan *sc_chan;
|
||||
struct mbox_client *cl;
|
||||
char *chan_name;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
sc_ipc = devm_kzalloc(dev, sizeof(*sc_ipc), GFP_KERNEL);
|
||||
if (!sc_ipc)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < SCU_MU_CHAN_NUM; i++) {
|
||||
if (i < 4)
|
||||
chan_name = kasprintf(GFP_KERNEL, "tx%d", i);
|
||||
else
|
||||
chan_name = kasprintf(GFP_KERNEL, "rx%d", i - 4);
|
||||
|
||||
if (!chan_name)
|
||||
return -ENOMEM;
|
||||
|
||||
sc_chan = &sc_ipc->chans[i];
|
||||
cl = &sc_chan->cl;
|
||||
cl->dev = dev;
|
||||
cl->tx_block = false;
|
||||
cl->knows_txdone = true;
|
||||
cl->rx_callback = imx_scu_rx_callback;
|
||||
|
||||
sc_chan->sc_ipc = sc_ipc;
|
||||
sc_chan->idx = i % 4;
|
||||
sc_chan->ch = mbox_request_channel_byname(cl, chan_name);
|
||||
if (IS_ERR(sc_chan->ch)) {
|
||||
ret = PTR_ERR(sc_chan->ch);
|
||||
if (ret != -EPROBE_DEFER)
|
||||
dev_err(dev, "Failed to request mbox chan %s ret %d\n",
|
||||
chan_name, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_dbg(dev, "request mbox chan %s\n", chan_name);
|
||||
/* chan_name is not used anymore by framework */
|
||||
kfree(chan_name);
|
||||
}
|
||||
|
||||
sc_ipc->dev = dev;
|
||||
mutex_init(&sc_ipc->lock);
|
||||
init_completion(&sc_ipc->done);
|
||||
|
||||
imx_sc_ipc_handle = sc_ipc;
|
||||
|
||||
dev_info(dev, "NXP i.MX SCU Initialized\n");
|
||||
|
||||
return devm_of_platform_populate(dev);
|
||||
}
|
||||
|
||||
static const struct of_device_id imx_scu_match[] = {
|
||||
{ .compatible = "fsl,imx-scu", },
|
||||
{ /* Sentinel */ }
|
||||
};
|
||||
|
||||
static struct platform_driver imx_scu_driver = {
|
||||
.driver = {
|
||||
.name = "imx-scu",
|
||||
.of_match_table = imx_scu_match,
|
||||
},
|
||||
.probe = imx_scu_probe,
|
||||
};
|
||||
builtin_platform_driver(imx_scu_driver);
|
||||
|
||||
MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
|
||||
MODULE_DESCRIPTION("IMX SCU firmware protocol driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017~2018 NXP
|
||||
* Author: Dong Aisheng <aisheng.dong@nxp.com>
|
||||
*
|
||||
* File containing client-side RPC functions for the MISC service. These
|
||||
* function are ported to clients that communicate to the SC.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/firmware/imx/svc/misc.h>
|
||||
|
||||
struct imx_sc_msg_req_misc_set_ctrl {
|
||||
struct imx_sc_rpc_msg hdr;
|
||||
u32 ctrl;
|
||||
u32 val;
|
||||
u16 resource;
|
||||
} __packed;
|
||||
|
||||
struct imx_sc_msg_req_misc_get_ctrl {
|
||||
struct imx_sc_rpc_msg hdr;
|
||||
u32 ctrl;
|
||||
u16 resource;
|
||||
} __packed;
|
||||
|
||||
struct imx_sc_msg_resp_misc_get_ctrl {
|
||||
struct imx_sc_rpc_msg hdr;
|
||||
u32 val;
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* This function sets a miscellaneous control value.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource resource the control is associated with
|
||||
* @param[in] ctrl control to change
|
||||
* @param[in] val value to apply to the control
|
||||
*
|
||||
* @return Returns 0 for success and < 0 for errors.
|
||||
*/
|
||||
|
||||
int imx_sc_misc_set_control(struct imx_sc_ipc *ipc, u32 resource,
|
||||
u8 ctrl, u32 val)
|
||||
{
|
||||
struct imx_sc_msg_req_misc_set_ctrl msg;
|
||||
struct imx_sc_rpc_msg *hdr = &msg.hdr;
|
||||
|
||||
hdr->ver = IMX_SC_RPC_VERSION;
|
||||
hdr->svc = (uint8_t)IMX_SC_RPC_SVC_MISC;
|
||||
hdr->func = (uint8_t)IMX_SC_MISC_FUNC_SET_CONTROL;
|
||||
hdr->size = 4;
|
||||
|
||||
msg.ctrl = ctrl;
|
||||
msg.val = val;
|
||||
msg.resource = resource;
|
||||
|
||||
return imx_scu_call_rpc(ipc, &msg, true);
|
||||
}
|
||||
EXPORT_SYMBOL(imx_sc_misc_set_control);
|
||||
|
||||
/*
|
||||
* This function gets a miscellaneous control value.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource resource the control is associated with
|
||||
* @param[in] ctrl control to get
|
||||
* @param[out] val pointer to return the control value
|
||||
*
|
||||
* @return Returns 0 for success and < 0 for errors.
|
||||
*/
|
||||
|
||||
int imx_sc_misc_get_control(struct imx_sc_ipc *ipc, u32 resource,
|
||||
u8 ctrl, u32 *val)
|
||||
{
|
||||
struct imx_sc_msg_req_misc_get_ctrl msg;
|
||||
struct imx_sc_msg_resp_misc_get_ctrl *resp;
|
||||
struct imx_sc_rpc_msg *hdr = &msg.hdr;
|
||||
int ret;
|
||||
|
||||
hdr->ver = IMX_SC_RPC_VERSION;
|
||||
hdr->svc = (uint8_t)IMX_SC_RPC_SVC_MISC;
|
||||
hdr->func = (uint8_t)IMX_SC_MISC_FUNC_GET_CONTROL;
|
||||
hdr->size = 3;
|
||||
|
||||
msg.ctrl = ctrl;
|
||||
msg.resource = resource;
|
||||
|
||||
ret = imx_scu_call_rpc(ipc, &msg, true);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
resp = (struct imx_sc_msg_resp_misc_get_ctrl *)&msg;
|
||||
if (val != NULL)
|
||||
*val = resp->val;
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(imx_sc_misc_get_control);
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* Header file for the IPC implementation.
|
||||
*/
|
||||
|
||||
#ifndef _SC_IPC_H
|
||||
#define _SC_IPC_H
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#define IMX_SC_RPC_VERSION 1
|
||||
#define IMX_SC_RPC_MAX_MSG 8
|
||||
|
||||
struct imx_sc_ipc;
|
||||
|
||||
enum imx_sc_rpc_svc {
|
||||
IMX_SC_RPC_SVC_UNKNOWN = 0,
|
||||
IMX_SC_RPC_SVC_RETURN = 1,
|
||||
IMX_SC_RPC_SVC_PM = 2,
|
||||
IMX_SC_RPC_SVC_RM = 3,
|
||||
IMX_SC_RPC_SVC_TIMER = 5,
|
||||
IMX_SC_RPC_SVC_PAD = 6,
|
||||
IMX_SC_RPC_SVC_MISC = 7,
|
||||
IMX_SC_RPC_SVC_IRQ = 8,
|
||||
IMX_SC_RPC_SVC_ABORT = 9
|
||||
};
|
||||
|
||||
struct imx_sc_rpc_msg {
|
||||
uint8_t ver;
|
||||
uint8_t size;
|
||||
uint8_t svc;
|
||||
uint8_t func;
|
||||
};
|
||||
|
||||
/*
|
||||
* This is an function to send an RPC message over an IPC channel.
|
||||
* It is called by client-side SCFW API function shims.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in,out] msg handle to a message
|
||||
* @param[in] have_resp response flag
|
||||
*
|
||||
* If have_resp is true then this function waits for a response
|
||||
* and returns the result in msg.
|
||||
*/
|
||||
int imx_scu_call_rpc(struct imx_sc_ipc *ipc, void *msg, bool have_resp);
|
||||
|
||||
/*
|
||||
* This function gets the default ipc handle used by SCU
|
||||
*
|
||||
* @param[out] ipc sc ipc handle
|
||||
*
|
||||
* @return Returns an error code (0 = success, failed if < 0)
|
||||
*/
|
||||
int imx_scu_get_handle(struct imx_sc_ipc **ipc);
|
||||
#endif /* _SC_IPC_H */
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017~2018 NXP
|
||||
*
|
||||
* Header file containing the public System Controller Interface (SCI)
|
||||
* definitions.
|
||||
*/
|
||||
|
||||
#ifndef _SC_SCI_H
|
||||
#define _SC_SCI_H
|
||||
|
||||
#include <linux/firmware/imx/ipc.h>
|
||||
#include <linux/firmware/imx/types.h>
|
||||
|
||||
#include <linux/firmware/imx/svc/misc.h>
|
||||
#endif /* _SC_SCI_H */
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017~2018 NXP
|
||||
*
|
||||
* Header file containing the public API for the System Controller (SC)
|
||||
* Miscellaneous (MISC) function.
|
||||
*
|
||||
* MISC_SVC (SVC) Miscellaneous Service
|
||||
*
|
||||
* Module for the Miscellaneous (MISC) service.
|
||||
*/
|
||||
|
||||
#ifndef _SC_MISC_API_H
|
||||
#define _SC_MISC_API_H
|
||||
|
||||
#include <linux/firmware/imx/sci.h>
|
||||
|
||||
/*
|
||||
* This type is used to indicate RPC MISC function calls.
|
||||
*/
|
||||
enum imx_misc_func {
|
||||
IMX_SC_MISC_FUNC_UNKNOWN = 0,
|
||||
IMX_SC_MISC_FUNC_SET_CONTROL = 1,
|
||||
IMX_SC_MISC_FUNC_GET_CONTROL = 2,
|
||||
IMX_SC_MISC_FUNC_SET_MAX_DMA_GROUP = 4,
|
||||
IMX_SC_MISC_FUNC_SET_DMA_GROUP = 5,
|
||||
IMX_SC_MISC_FUNC_SECO_IMAGE_LOAD = 8,
|
||||
IMX_SC_MISC_FUNC_SECO_AUTHENTICATE = 9,
|
||||
IMX_SC_MISC_FUNC_DEBUG_OUT = 10,
|
||||
IMX_SC_MISC_FUNC_WAVEFORM_CAPTURE = 6,
|
||||
IMX_SC_MISC_FUNC_BUILD_INFO = 15,
|
||||
IMX_SC_MISC_FUNC_UNIQUE_ID = 19,
|
||||
IMX_SC_MISC_FUNC_SET_ARI = 3,
|
||||
IMX_SC_MISC_FUNC_BOOT_STATUS = 7,
|
||||
IMX_SC_MISC_FUNC_BOOT_DONE = 14,
|
||||
IMX_SC_MISC_FUNC_OTP_FUSE_READ = 11,
|
||||
IMX_SC_MISC_FUNC_OTP_FUSE_WRITE = 17,
|
||||
IMX_SC_MISC_FUNC_SET_TEMP = 12,
|
||||
IMX_SC_MISC_FUNC_GET_TEMP = 13,
|
||||
IMX_SC_MISC_FUNC_GET_BOOT_DEV = 16,
|
||||
IMX_SC_MISC_FUNC_GET_BUTTON_STATUS = 18,
|
||||
};
|
||||
|
||||
/*
|
||||
* Control Functions
|
||||
*/
|
||||
|
||||
int imx_sc_misc_set_control(struct imx_sc_ipc *ipc, u32 resource,
|
||||
u8 ctrl, u32 val);
|
||||
|
||||
int imx_sc_misc_get_control(struct imx_sc_ipc *ipc, u32 resource,
|
||||
u8 ctrl, u32 *val);
|
||||
|
||||
#endif /* _SC_MISC_API_H */
|
||||
|
|
@ -0,0 +1,617 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017~2018 NXP
|
||||
*
|
||||
* Header file containing types used across multiple service APIs.
|
||||
*/
|
||||
|
||||
#ifndef _SC_TYPES_H
|
||||
#define _SC_TYPES_H
|
||||
|
||||
/*
|
||||
* This type is used to indicate a resource. Resources include peripherals
|
||||
* and bus masters (but not memory regions). Note items from list should
|
||||
* never be changed or removed (only added to at the end of the list).
|
||||
*/
|
||||
enum imx_sc_rsrc {
|
||||
IMX_SC_R_A53 = 0,
|
||||
IMX_SC_R_A53_0 = 1,
|
||||
IMX_SC_R_A53_1 = 2,
|
||||
IMX_SC_R_A53_2 = 3,
|
||||
IMX_SC_R_A53_3 = 4,
|
||||
IMX_SC_R_A72 = 5,
|
||||
IMX_SC_R_A72_0 = 6,
|
||||
IMX_SC_R_A72_1 = 7,
|
||||
IMX_SC_R_A72_2 = 8,
|
||||
IMX_SC_R_A72_3 = 9,
|
||||
IMX_SC_R_CCI = 10,
|
||||
IMX_SC_R_DB = 11,
|
||||
IMX_SC_R_DRC_0 = 12,
|
||||
IMX_SC_R_DRC_1 = 13,
|
||||
IMX_SC_R_GIC_SMMU = 14,
|
||||
IMX_SC_R_IRQSTR_M4_0 = 15,
|
||||
IMX_SC_R_IRQSTR_M4_1 = 16,
|
||||
IMX_SC_R_SMMU = 17,
|
||||
IMX_SC_R_GIC = 18,
|
||||
IMX_SC_R_DC_0_BLIT0 = 19,
|
||||
IMX_SC_R_DC_0_BLIT1 = 20,
|
||||
IMX_SC_R_DC_0_BLIT2 = 21,
|
||||
IMX_SC_R_DC_0_BLIT_OUT = 22,
|
||||
IMX_SC_R_DC_0_CAPTURE0 = 23,
|
||||
IMX_SC_R_DC_0_CAPTURE1 = 24,
|
||||
IMX_SC_R_DC_0_WARP = 25,
|
||||
IMX_SC_R_DC_0_INTEGRAL0 = 26,
|
||||
IMX_SC_R_DC_0_INTEGRAL1 = 27,
|
||||
IMX_SC_R_DC_0_VIDEO0 = 28,
|
||||
IMX_SC_R_DC_0_VIDEO1 = 29,
|
||||
IMX_SC_R_DC_0_FRAC0 = 30,
|
||||
IMX_SC_R_DC_0_FRAC1 = 31,
|
||||
IMX_SC_R_DC_0 = 32,
|
||||
IMX_SC_R_GPU_2_PID0 = 33,
|
||||
IMX_SC_R_DC_0_PLL_0 = 34,
|
||||
IMX_SC_R_DC_0_PLL_1 = 35,
|
||||
IMX_SC_R_DC_1_BLIT0 = 36,
|
||||
IMX_SC_R_DC_1_BLIT1 = 37,
|
||||
IMX_SC_R_DC_1_BLIT2 = 38,
|
||||
IMX_SC_R_DC_1_BLIT_OUT = 39,
|
||||
IMX_SC_R_DC_1_CAPTURE0 = 40,
|
||||
IMX_SC_R_DC_1_CAPTURE1 = 41,
|
||||
IMX_SC_R_DC_1_WARP = 42,
|
||||
IMX_SC_R_DC_1_INTEGRAL0 = 43,
|
||||
IMX_SC_R_DC_1_INTEGRAL1 = 44,
|
||||
IMX_SC_R_DC_1_VIDEO0 = 45,
|
||||
IMX_SC_R_DC_1_VIDEO1 = 46,
|
||||
IMX_SC_R_DC_1_FRAC0 = 47,
|
||||
IMX_SC_R_DC_1_FRAC1 = 48,
|
||||
IMX_SC_R_DC_1 = 49,
|
||||
IMX_SC_R_GPU_3_PID0 = 50,
|
||||
IMX_SC_R_DC_1_PLL_0 = 51,
|
||||
IMX_SC_R_DC_1_PLL_1 = 52,
|
||||
IMX_SC_R_SPI_0 = 53,
|
||||
IMX_SC_R_SPI_1 = 54,
|
||||
IMX_SC_R_SPI_2 = 55,
|
||||
IMX_SC_R_SPI_3 = 56,
|
||||
IMX_SC_R_UART_0 = 57,
|
||||
IMX_SC_R_UART_1 = 58,
|
||||
IMX_SC_R_UART_2 = 59,
|
||||
IMX_SC_R_UART_3 = 60,
|
||||
IMX_SC_R_UART_4 = 61,
|
||||
IMX_SC_R_EMVSIM_0 = 62,
|
||||
IMX_SC_R_EMVSIM_1 = 63,
|
||||
IMX_SC_R_DMA_0_CH0 = 64,
|
||||
IMX_SC_R_DMA_0_CH1 = 65,
|
||||
IMX_SC_R_DMA_0_CH2 = 66,
|
||||
IMX_SC_R_DMA_0_CH3 = 67,
|
||||
IMX_SC_R_DMA_0_CH4 = 68,
|
||||
IMX_SC_R_DMA_0_CH5 = 69,
|
||||
IMX_SC_R_DMA_0_CH6 = 70,
|
||||
IMX_SC_R_DMA_0_CH7 = 71,
|
||||
IMX_SC_R_DMA_0_CH8 = 72,
|
||||
IMX_SC_R_DMA_0_CH9 = 73,
|
||||
IMX_SC_R_DMA_0_CH10 = 74,
|
||||
IMX_SC_R_DMA_0_CH11 = 75,
|
||||
IMX_SC_R_DMA_0_CH12 = 76,
|
||||
IMX_SC_R_DMA_0_CH13 = 77,
|
||||
IMX_SC_R_DMA_0_CH14 = 78,
|
||||
IMX_SC_R_DMA_0_CH15 = 79,
|
||||
IMX_SC_R_DMA_0_CH16 = 80,
|
||||
IMX_SC_R_DMA_0_CH17 = 81,
|
||||
IMX_SC_R_DMA_0_CH18 = 82,
|
||||
IMX_SC_R_DMA_0_CH19 = 83,
|
||||
IMX_SC_R_DMA_0_CH20 = 84,
|
||||
IMX_SC_R_DMA_0_CH21 = 85,
|
||||
IMX_SC_R_DMA_0_CH22 = 86,
|
||||
IMX_SC_R_DMA_0_CH23 = 87,
|
||||
IMX_SC_R_DMA_0_CH24 = 88,
|
||||
IMX_SC_R_DMA_0_CH25 = 89,
|
||||
IMX_SC_R_DMA_0_CH26 = 90,
|
||||
IMX_SC_R_DMA_0_CH27 = 91,
|
||||
IMX_SC_R_DMA_0_CH28 = 92,
|
||||
IMX_SC_R_DMA_0_CH29 = 93,
|
||||
IMX_SC_R_DMA_0_CH30 = 94,
|
||||
IMX_SC_R_DMA_0_CH31 = 95,
|
||||
IMX_SC_R_I2C_0 = 96,
|
||||
IMX_SC_R_I2C_1 = 97,
|
||||
IMX_SC_R_I2C_2 = 98,
|
||||
IMX_SC_R_I2C_3 = 99,
|
||||
IMX_SC_R_I2C_4 = 100,
|
||||
IMX_SC_R_ADC_0 = 101,
|
||||
IMX_SC_R_ADC_1 = 102,
|
||||
IMX_SC_R_FTM_0 = 103,
|
||||
IMX_SC_R_FTM_1 = 104,
|
||||
IMX_SC_R_CAN_0 = 105,
|
||||
IMX_SC_R_CAN_1 = 106,
|
||||
IMX_SC_R_CAN_2 = 107,
|
||||
IMX_SC_R_DMA_1_CH0 = 108,
|
||||
IMX_SC_R_DMA_1_CH1 = 109,
|
||||
IMX_SC_R_DMA_1_CH2 = 110,
|
||||
IMX_SC_R_DMA_1_CH3 = 111,
|
||||
IMX_SC_R_DMA_1_CH4 = 112,
|
||||
IMX_SC_R_DMA_1_CH5 = 113,
|
||||
IMX_SC_R_DMA_1_CH6 = 114,
|
||||
IMX_SC_R_DMA_1_CH7 = 115,
|
||||
IMX_SC_R_DMA_1_CH8 = 116,
|
||||
IMX_SC_R_DMA_1_CH9 = 117,
|
||||
IMX_SC_R_DMA_1_CH10 = 118,
|
||||
IMX_SC_R_DMA_1_CH11 = 119,
|
||||
IMX_SC_R_DMA_1_CH12 = 120,
|
||||
IMX_SC_R_DMA_1_CH13 = 121,
|
||||
IMX_SC_R_DMA_1_CH14 = 122,
|
||||
IMX_SC_R_DMA_1_CH15 = 123,
|
||||
IMX_SC_R_DMA_1_CH16 = 124,
|
||||
IMX_SC_R_DMA_1_CH17 = 125,
|
||||
IMX_SC_R_DMA_1_CH18 = 126,
|
||||
IMX_SC_R_DMA_1_CH19 = 127,
|
||||
IMX_SC_R_DMA_1_CH20 = 128,
|
||||
IMX_SC_R_DMA_1_CH21 = 129,
|
||||
IMX_SC_R_DMA_1_CH22 = 130,
|
||||
IMX_SC_R_DMA_1_CH23 = 131,
|
||||
IMX_SC_R_DMA_1_CH24 = 132,
|
||||
IMX_SC_R_DMA_1_CH25 = 133,
|
||||
IMX_SC_R_DMA_1_CH26 = 134,
|
||||
IMX_SC_R_DMA_1_CH27 = 135,
|
||||
IMX_SC_R_DMA_1_CH28 = 136,
|
||||
IMX_SC_R_DMA_1_CH29 = 137,
|
||||
IMX_SC_R_DMA_1_CH30 = 138,
|
||||
IMX_SC_R_DMA_1_CH31 = 139,
|
||||
IMX_SC_R_UNUSED1 = 140,
|
||||
IMX_SC_R_UNUSED2 = 141,
|
||||
IMX_SC_R_UNUSED3 = 142,
|
||||
IMX_SC_R_UNUSED4 = 143,
|
||||
IMX_SC_R_GPU_0_PID0 = 144,
|
||||
IMX_SC_R_GPU_0_PID1 = 145,
|
||||
IMX_SC_R_GPU_0_PID2 = 146,
|
||||
IMX_SC_R_GPU_0_PID3 = 147,
|
||||
IMX_SC_R_GPU_1_PID0 = 148,
|
||||
IMX_SC_R_GPU_1_PID1 = 149,
|
||||
IMX_SC_R_GPU_1_PID2 = 150,
|
||||
IMX_SC_R_GPU_1_PID3 = 151,
|
||||
IMX_SC_R_PCIE_A = 152,
|
||||
IMX_SC_R_SERDES_0 = 153,
|
||||
IMX_SC_R_MATCH_0 = 154,
|
||||
IMX_SC_R_MATCH_1 = 155,
|
||||
IMX_SC_R_MATCH_2 = 156,
|
||||
IMX_SC_R_MATCH_3 = 157,
|
||||
IMX_SC_R_MATCH_4 = 158,
|
||||
IMX_SC_R_MATCH_5 = 159,
|
||||
IMX_SC_R_MATCH_6 = 160,
|
||||
IMX_SC_R_MATCH_7 = 161,
|
||||
IMX_SC_R_MATCH_8 = 162,
|
||||
IMX_SC_R_MATCH_9 = 163,
|
||||
IMX_SC_R_MATCH_10 = 164,
|
||||
IMX_SC_R_MATCH_11 = 165,
|
||||
IMX_SC_R_MATCH_12 = 166,
|
||||
IMX_SC_R_MATCH_13 = 167,
|
||||
IMX_SC_R_MATCH_14 = 168,
|
||||
IMX_SC_R_PCIE_B = 169,
|
||||
IMX_SC_R_SATA_0 = 170,
|
||||
IMX_SC_R_SERDES_1 = 171,
|
||||
IMX_SC_R_HSIO_GPIO = 172,
|
||||
IMX_SC_R_MATCH_15 = 173,
|
||||
IMX_SC_R_MATCH_16 = 174,
|
||||
IMX_SC_R_MATCH_17 = 175,
|
||||
IMX_SC_R_MATCH_18 = 176,
|
||||
IMX_SC_R_MATCH_19 = 177,
|
||||
IMX_SC_R_MATCH_20 = 178,
|
||||
IMX_SC_R_MATCH_21 = 179,
|
||||
IMX_SC_R_MATCH_22 = 180,
|
||||
IMX_SC_R_MATCH_23 = 181,
|
||||
IMX_SC_R_MATCH_24 = 182,
|
||||
IMX_SC_R_MATCH_25 = 183,
|
||||
IMX_SC_R_MATCH_26 = 184,
|
||||
IMX_SC_R_MATCH_27 = 185,
|
||||
IMX_SC_R_MATCH_28 = 186,
|
||||
IMX_SC_R_LCD_0 = 187,
|
||||
IMX_SC_R_LCD_0_PWM_0 = 188,
|
||||
IMX_SC_R_LCD_0_I2C_0 = 189,
|
||||
IMX_SC_R_LCD_0_I2C_1 = 190,
|
||||
IMX_SC_R_PWM_0 = 191,
|
||||
IMX_SC_R_PWM_1 = 192,
|
||||
IMX_SC_R_PWM_2 = 193,
|
||||
IMX_SC_R_PWM_3 = 194,
|
||||
IMX_SC_R_PWM_4 = 195,
|
||||
IMX_SC_R_PWM_5 = 196,
|
||||
IMX_SC_R_PWM_6 = 197,
|
||||
IMX_SC_R_PWM_7 = 198,
|
||||
IMX_SC_R_GPIO_0 = 199,
|
||||
IMX_SC_R_GPIO_1 = 200,
|
||||
IMX_SC_R_GPIO_2 = 201,
|
||||
IMX_SC_R_GPIO_3 = 202,
|
||||
IMX_SC_R_GPIO_4 = 203,
|
||||
IMX_SC_R_GPIO_5 = 204,
|
||||
IMX_SC_R_GPIO_6 = 205,
|
||||
IMX_SC_R_GPIO_7 = 206,
|
||||
IMX_SC_R_GPT_0 = 207,
|
||||
IMX_SC_R_GPT_1 = 208,
|
||||
IMX_SC_R_GPT_2 = 209,
|
||||
IMX_SC_R_GPT_3 = 210,
|
||||
IMX_SC_R_GPT_4 = 211,
|
||||
IMX_SC_R_KPP = 212,
|
||||
IMX_SC_R_MU_0A = 213,
|
||||
IMX_SC_R_MU_1A = 214,
|
||||
IMX_SC_R_MU_2A = 215,
|
||||
IMX_SC_R_MU_3A = 216,
|
||||
IMX_SC_R_MU_4A = 217,
|
||||
IMX_SC_R_MU_5A = 218,
|
||||
IMX_SC_R_MU_6A = 219,
|
||||
IMX_SC_R_MU_7A = 220,
|
||||
IMX_SC_R_MU_8A = 221,
|
||||
IMX_SC_R_MU_9A = 222,
|
||||
IMX_SC_R_MU_10A = 223,
|
||||
IMX_SC_R_MU_11A = 224,
|
||||
IMX_SC_R_MU_12A = 225,
|
||||
IMX_SC_R_MU_13A = 226,
|
||||
IMX_SC_R_MU_5B = 227,
|
||||
IMX_SC_R_MU_6B = 228,
|
||||
IMX_SC_R_MU_7B = 229,
|
||||
IMX_SC_R_MU_8B = 230,
|
||||
IMX_SC_R_MU_9B = 231,
|
||||
IMX_SC_R_MU_10B = 232,
|
||||
IMX_SC_R_MU_11B = 233,
|
||||
IMX_SC_R_MU_12B = 234,
|
||||
IMX_SC_R_MU_13B = 235,
|
||||
IMX_SC_R_ROM_0 = 236,
|
||||
IMX_SC_R_FSPI_0 = 237,
|
||||
IMX_SC_R_FSPI_1 = 238,
|
||||
IMX_SC_R_IEE = 239,
|
||||
IMX_SC_R_IEE_R0 = 240,
|
||||
IMX_SC_R_IEE_R1 = 241,
|
||||
IMX_SC_R_IEE_R2 = 242,
|
||||
IMX_SC_R_IEE_R3 = 243,
|
||||
IMX_SC_R_IEE_R4 = 244,
|
||||
IMX_SC_R_IEE_R5 = 245,
|
||||
IMX_SC_R_IEE_R6 = 246,
|
||||
IMX_SC_R_IEE_R7 = 247,
|
||||
IMX_SC_R_SDHC_0 = 248,
|
||||
IMX_SC_R_SDHC_1 = 249,
|
||||
IMX_SC_R_SDHC_2 = 250,
|
||||
IMX_SC_R_ENET_0 = 251,
|
||||
IMX_SC_R_ENET_1 = 252,
|
||||
IMX_SC_R_MLB_0 = 253,
|
||||
IMX_SC_R_DMA_2_CH0 = 254,
|
||||
IMX_SC_R_DMA_2_CH1 = 255,
|
||||
IMX_SC_R_DMA_2_CH2 = 256,
|
||||
IMX_SC_R_DMA_2_CH3 = 257,
|
||||
IMX_SC_R_DMA_2_CH4 = 258,
|
||||
IMX_SC_R_USB_0 = 259,
|
||||
IMX_SC_R_USB_1 = 260,
|
||||
IMX_SC_R_USB_0_PHY = 261,
|
||||
IMX_SC_R_USB_2 = 262,
|
||||
IMX_SC_R_USB_2_PHY = 263,
|
||||
IMX_SC_R_DTCP = 264,
|
||||
IMX_SC_R_NAND = 265,
|
||||
IMX_SC_R_LVDS_0 = 266,
|
||||
IMX_SC_R_LVDS_0_PWM_0 = 267,
|
||||
IMX_SC_R_LVDS_0_I2C_0 = 268,
|
||||
IMX_SC_R_LVDS_0_I2C_1 = 269,
|
||||
IMX_SC_R_LVDS_1 = 270,
|
||||
IMX_SC_R_LVDS_1_PWM_0 = 271,
|
||||
IMX_SC_R_LVDS_1_I2C_0 = 272,
|
||||
IMX_SC_R_LVDS_1_I2C_1 = 273,
|
||||
IMX_SC_R_LVDS_2 = 274,
|
||||
IMX_SC_R_LVDS_2_PWM_0 = 275,
|
||||
IMX_SC_R_LVDS_2_I2C_0 = 276,
|
||||
IMX_SC_R_LVDS_2_I2C_1 = 277,
|
||||
IMX_SC_R_M4_0_PID0 = 278,
|
||||
IMX_SC_R_M4_0_PID1 = 279,
|
||||
IMX_SC_R_M4_0_PID2 = 280,
|
||||
IMX_SC_R_M4_0_PID3 = 281,
|
||||
IMX_SC_R_M4_0_PID4 = 282,
|
||||
IMX_SC_R_M4_0_RGPIO = 283,
|
||||
IMX_SC_R_M4_0_SEMA42 = 284,
|
||||
IMX_SC_R_M4_0_TPM = 285,
|
||||
IMX_SC_R_M4_0_PIT = 286,
|
||||
IMX_SC_R_M4_0_UART = 287,
|
||||
IMX_SC_R_M4_0_I2C = 288,
|
||||
IMX_SC_R_M4_0_INTMUX = 289,
|
||||
IMX_SC_R_M4_0_SIM = 290,
|
||||
IMX_SC_R_M4_0_WDOG = 291,
|
||||
IMX_SC_R_M4_0_MU_0B = 292,
|
||||
IMX_SC_R_M4_0_MU_0A0 = 293,
|
||||
IMX_SC_R_M4_0_MU_0A1 = 294,
|
||||
IMX_SC_R_M4_0_MU_0A2 = 295,
|
||||
IMX_SC_R_M4_0_MU_0A3 = 296,
|
||||
IMX_SC_R_M4_0_MU_1A = 297,
|
||||
IMX_SC_R_M4_1_PID0 = 298,
|
||||
IMX_SC_R_M4_1_PID1 = 299,
|
||||
IMX_SC_R_M4_1_PID2 = 300,
|
||||
IMX_SC_R_M4_1_PID3 = 301,
|
||||
IMX_SC_R_M4_1_PID4 = 302,
|
||||
IMX_SC_R_M4_1_RGPIO = 303,
|
||||
IMX_SC_R_M4_1_SEMA42 = 304,
|
||||
IMX_SC_R_M4_1_TPM = 305,
|
||||
IMX_SC_R_M4_1_PIT = 306,
|
||||
IMX_SC_R_M4_1_UART = 307,
|
||||
IMX_SC_R_M4_1_I2C = 308,
|
||||
IMX_SC_R_M4_1_INTMUX = 309,
|
||||
IMX_SC_R_M4_1_SIM = 310,
|
||||
IMX_SC_R_M4_1_WDOG = 311,
|
||||
IMX_SC_R_M4_1_MU_0B = 312,
|
||||
IMX_SC_R_M4_1_MU_0A0 = 313,
|
||||
IMX_SC_R_M4_1_MU_0A1 = 314,
|
||||
IMX_SC_R_M4_1_MU_0A2 = 315,
|
||||
IMX_SC_R_M4_1_MU_0A3 = 316,
|
||||
IMX_SC_R_M4_1_MU_1A = 317,
|
||||
IMX_SC_R_SAI_0 = 318,
|
||||
IMX_SC_R_SAI_1 = 319,
|
||||
IMX_SC_R_SAI_2 = 320,
|
||||
IMX_SC_R_IRQSTR_SCU2 = 321,
|
||||
IMX_SC_R_IRQSTR_DSP = 322,
|
||||
IMX_SC_R_UNUSED5 = 323,
|
||||
IMX_SC_R_UNUSED6 = 324,
|
||||
IMX_SC_R_AUDIO_PLL_0 = 325,
|
||||
IMX_SC_R_PI_0 = 326,
|
||||
IMX_SC_R_PI_0_PWM_0 = 327,
|
||||
IMX_SC_R_PI_0_PWM_1 = 328,
|
||||
IMX_SC_R_PI_0_I2C_0 = 329,
|
||||
IMX_SC_R_PI_0_PLL = 330,
|
||||
IMX_SC_R_PI_1 = 331,
|
||||
IMX_SC_R_PI_1_PWM_0 = 332,
|
||||
IMX_SC_R_PI_1_PWM_1 = 333,
|
||||
IMX_SC_R_PI_1_I2C_0 = 334,
|
||||
IMX_SC_R_PI_1_PLL = 335,
|
||||
IMX_SC_R_SC_PID0 = 336,
|
||||
IMX_SC_R_SC_PID1 = 337,
|
||||
IMX_SC_R_SC_PID2 = 338,
|
||||
IMX_SC_R_SC_PID3 = 339,
|
||||
IMX_SC_R_SC_PID4 = 340,
|
||||
IMX_SC_R_SC_SEMA42 = 341,
|
||||
IMX_SC_R_SC_TPM = 342,
|
||||
IMX_SC_R_SC_PIT = 343,
|
||||
IMX_SC_R_SC_UART = 344,
|
||||
IMX_SC_R_SC_I2C = 345,
|
||||
IMX_SC_R_SC_MU_0B = 346,
|
||||
IMX_SC_R_SC_MU_0A0 = 347,
|
||||
IMX_SC_R_SC_MU_0A1 = 348,
|
||||
IMX_SC_R_SC_MU_0A2 = 349,
|
||||
IMX_SC_R_SC_MU_0A3 = 350,
|
||||
IMX_SC_R_SC_MU_1A = 351,
|
||||
IMX_SC_R_SYSCNT_RD = 352,
|
||||
IMX_SC_R_SYSCNT_CMP = 353,
|
||||
IMX_SC_R_DEBUG = 354,
|
||||
IMX_SC_R_SYSTEM = 355,
|
||||
IMX_SC_R_SNVS = 356,
|
||||
IMX_SC_R_OTP = 357,
|
||||
IMX_SC_R_VPU_PID0 = 358,
|
||||
IMX_SC_R_VPU_PID1 = 359,
|
||||
IMX_SC_R_VPU_PID2 = 360,
|
||||
IMX_SC_R_VPU_PID3 = 361,
|
||||
IMX_SC_R_VPU_PID4 = 362,
|
||||
IMX_SC_R_VPU_PID5 = 363,
|
||||
IMX_SC_R_VPU_PID6 = 364,
|
||||
IMX_SC_R_VPU_PID7 = 365,
|
||||
IMX_SC_R_VPU_UART = 366,
|
||||
IMX_SC_R_VPUCORE = 367,
|
||||
IMX_SC_R_VPUCORE_0 = 368,
|
||||
IMX_SC_R_VPUCORE_1 = 369,
|
||||
IMX_SC_R_VPUCORE_2 = 370,
|
||||
IMX_SC_R_VPUCORE_3 = 371,
|
||||
IMX_SC_R_DMA_4_CH0 = 372,
|
||||
IMX_SC_R_DMA_4_CH1 = 373,
|
||||
IMX_SC_R_DMA_4_CH2 = 374,
|
||||
IMX_SC_R_DMA_4_CH3 = 375,
|
||||
IMX_SC_R_DMA_4_CH4 = 376,
|
||||
IMX_SC_R_ISI_CH0 = 377,
|
||||
IMX_SC_R_ISI_CH1 = 378,
|
||||
IMX_SC_R_ISI_CH2 = 379,
|
||||
IMX_SC_R_ISI_CH3 = 380,
|
||||
IMX_SC_R_ISI_CH4 = 381,
|
||||
IMX_SC_R_ISI_CH5 = 382,
|
||||
IMX_SC_R_ISI_CH6 = 383,
|
||||
IMX_SC_R_ISI_CH7 = 384,
|
||||
IMX_SC_R_MJPEG_DEC_S0 = 385,
|
||||
IMX_SC_R_MJPEG_DEC_S1 = 386,
|
||||
IMX_SC_R_MJPEG_DEC_S2 = 387,
|
||||
IMX_SC_R_MJPEG_DEC_S3 = 388,
|
||||
IMX_SC_R_MJPEG_ENC_S0 = 389,
|
||||
IMX_SC_R_MJPEG_ENC_S1 = 390,
|
||||
IMX_SC_R_MJPEG_ENC_S2 = 391,
|
||||
IMX_SC_R_MJPEG_ENC_S3 = 392,
|
||||
IMX_SC_R_MIPI_0 = 393,
|
||||
IMX_SC_R_MIPI_0_PWM_0 = 394,
|
||||
IMX_SC_R_MIPI_0_I2C_0 = 395,
|
||||
IMX_SC_R_MIPI_0_I2C_1 = 396,
|
||||
IMX_SC_R_MIPI_1 = 397,
|
||||
IMX_SC_R_MIPI_1_PWM_0 = 398,
|
||||
IMX_SC_R_MIPI_1_I2C_0 = 399,
|
||||
IMX_SC_R_MIPI_1_I2C_1 = 400,
|
||||
IMX_SC_R_CSI_0 = 401,
|
||||
IMX_SC_R_CSI_0_PWM_0 = 402,
|
||||
IMX_SC_R_CSI_0_I2C_0 = 403,
|
||||
IMX_SC_R_CSI_1 = 404,
|
||||
IMX_SC_R_CSI_1_PWM_0 = 405,
|
||||
IMX_SC_R_CSI_1_I2C_0 = 406,
|
||||
IMX_SC_R_HDMI = 407,
|
||||
IMX_SC_R_HDMI_I2S = 408,
|
||||
IMX_SC_R_HDMI_I2C_0 = 409,
|
||||
IMX_SC_R_HDMI_PLL_0 = 410,
|
||||
IMX_SC_R_HDMI_RX = 411,
|
||||
IMX_SC_R_HDMI_RX_BYPASS = 412,
|
||||
IMX_SC_R_HDMI_RX_I2C_0 = 413,
|
||||
IMX_SC_R_ASRC_0 = 414,
|
||||
IMX_SC_R_ESAI_0 = 415,
|
||||
IMX_SC_R_SPDIF_0 = 416,
|
||||
IMX_SC_R_SPDIF_1 = 417,
|
||||
IMX_SC_R_SAI_3 = 418,
|
||||
IMX_SC_R_SAI_4 = 419,
|
||||
IMX_SC_R_SAI_5 = 420,
|
||||
IMX_SC_R_GPT_5 = 421,
|
||||
IMX_SC_R_GPT_6 = 422,
|
||||
IMX_SC_R_GPT_7 = 423,
|
||||
IMX_SC_R_GPT_8 = 424,
|
||||
IMX_SC_R_GPT_9 = 425,
|
||||
IMX_SC_R_GPT_10 = 426,
|
||||
IMX_SC_R_DMA_2_CH5 = 427,
|
||||
IMX_SC_R_DMA_2_CH6 = 428,
|
||||
IMX_SC_R_DMA_2_CH7 = 429,
|
||||
IMX_SC_R_DMA_2_CH8 = 430,
|
||||
IMX_SC_R_DMA_2_CH9 = 431,
|
||||
IMX_SC_R_DMA_2_CH10 = 432,
|
||||
IMX_SC_R_DMA_2_CH11 = 433,
|
||||
IMX_SC_R_DMA_2_CH12 = 434,
|
||||
IMX_SC_R_DMA_2_CH13 = 435,
|
||||
IMX_SC_R_DMA_2_CH14 = 436,
|
||||
IMX_SC_R_DMA_2_CH15 = 437,
|
||||
IMX_SC_R_DMA_2_CH16 = 438,
|
||||
IMX_SC_R_DMA_2_CH17 = 439,
|
||||
IMX_SC_R_DMA_2_CH18 = 440,
|
||||
IMX_SC_R_DMA_2_CH19 = 441,
|
||||
IMX_SC_R_DMA_2_CH20 = 442,
|
||||
IMX_SC_R_DMA_2_CH21 = 443,
|
||||
IMX_SC_R_DMA_2_CH22 = 444,
|
||||
IMX_SC_R_DMA_2_CH23 = 445,
|
||||
IMX_SC_R_DMA_2_CH24 = 446,
|
||||
IMX_SC_R_DMA_2_CH25 = 447,
|
||||
IMX_SC_R_DMA_2_CH26 = 448,
|
||||
IMX_SC_R_DMA_2_CH27 = 449,
|
||||
IMX_SC_R_DMA_2_CH28 = 450,
|
||||
IMX_SC_R_DMA_2_CH29 = 451,
|
||||
IMX_SC_R_DMA_2_CH30 = 452,
|
||||
IMX_SC_R_DMA_2_CH31 = 453,
|
||||
IMX_SC_R_ASRC_1 = 454,
|
||||
IMX_SC_R_ESAI_1 = 455,
|
||||
IMX_SC_R_SAI_6 = 456,
|
||||
IMX_SC_R_SAI_7 = 457,
|
||||
IMX_SC_R_AMIX = 458,
|
||||
IMX_SC_R_MQS_0 = 459,
|
||||
IMX_SC_R_DMA_3_CH0 = 460,
|
||||
IMX_SC_R_DMA_3_CH1 = 461,
|
||||
IMX_SC_R_DMA_3_CH2 = 462,
|
||||
IMX_SC_R_DMA_3_CH3 = 463,
|
||||
IMX_SC_R_DMA_3_CH4 = 464,
|
||||
IMX_SC_R_DMA_3_CH5 = 465,
|
||||
IMX_SC_R_DMA_3_CH6 = 466,
|
||||
IMX_SC_R_DMA_3_CH7 = 467,
|
||||
IMX_SC_R_DMA_3_CH8 = 468,
|
||||
IMX_SC_R_DMA_3_CH9 = 469,
|
||||
IMX_SC_R_DMA_3_CH10 = 470,
|
||||
IMX_SC_R_DMA_3_CH11 = 471,
|
||||
IMX_SC_R_DMA_3_CH12 = 472,
|
||||
IMX_SC_R_DMA_3_CH13 = 473,
|
||||
IMX_SC_R_DMA_3_CH14 = 474,
|
||||
IMX_SC_R_DMA_3_CH15 = 475,
|
||||
IMX_SC_R_DMA_3_CH16 = 476,
|
||||
IMX_SC_R_DMA_3_CH17 = 477,
|
||||
IMX_SC_R_DMA_3_CH18 = 478,
|
||||
IMX_SC_R_DMA_3_CH19 = 479,
|
||||
IMX_SC_R_DMA_3_CH20 = 480,
|
||||
IMX_SC_R_DMA_3_CH21 = 481,
|
||||
IMX_SC_R_DMA_3_CH22 = 482,
|
||||
IMX_SC_R_DMA_3_CH23 = 483,
|
||||
IMX_SC_R_DMA_3_CH24 = 484,
|
||||
IMX_SC_R_DMA_3_CH25 = 485,
|
||||
IMX_SC_R_DMA_3_CH26 = 486,
|
||||
IMX_SC_R_DMA_3_CH27 = 487,
|
||||
IMX_SC_R_DMA_3_CH28 = 488,
|
||||
IMX_SC_R_DMA_3_CH29 = 489,
|
||||
IMX_SC_R_DMA_3_CH30 = 490,
|
||||
IMX_SC_R_DMA_3_CH31 = 491,
|
||||
IMX_SC_R_AUDIO_PLL_1 = 492,
|
||||
IMX_SC_R_AUDIO_CLK_0 = 493,
|
||||
IMX_SC_R_AUDIO_CLK_1 = 494,
|
||||
IMX_SC_R_MCLK_OUT_0 = 495,
|
||||
IMX_SC_R_MCLK_OUT_1 = 496,
|
||||
IMX_SC_R_PMIC_0 = 497,
|
||||
IMX_SC_R_PMIC_1 = 498,
|
||||
IMX_SC_R_SECO = 499,
|
||||
IMX_SC_R_CAAM_JR1 = 500,
|
||||
IMX_SC_R_CAAM_JR2 = 501,
|
||||
IMX_SC_R_CAAM_JR3 = 502,
|
||||
IMX_SC_R_SECO_MU_2 = 503,
|
||||
IMX_SC_R_SECO_MU_3 = 504,
|
||||
IMX_SC_R_SECO_MU_4 = 505,
|
||||
IMX_SC_R_HDMI_RX_PWM_0 = 506,
|
||||
IMX_SC_R_A35 = 507,
|
||||
IMX_SC_R_A35_0 = 508,
|
||||
IMX_SC_R_A35_1 = 509,
|
||||
IMX_SC_R_A35_2 = 510,
|
||||
IMX_SC_R_A35_3 = 511,
|
||||
IMX_SC_R_DSP = 512,
|
||||
IMX_SC_R_DSP_RAM = 513,
|
||||
IMX_SC_R_CAAM_JR1_OUT = 514,
|
||||
IMX_SC_R_CAAM_JR2_OUT = 515,
|
||||
IMX_SC_R_CAAM_JR3_OUT = 516,
|
||||
IMX_SC_R_VPU_DEC_0 = 517,
|
||||
IMX_SC_R_VPU_ENC_0 = 518,
|
||||
IMX_SC_R_CAAM_JR0 = 519,
|
||||
IMX_SC_R_CAAM_JR0_OUT = 520,
|
||||
IMX_SC_R_PMIC_2 = 521,
|
||||
IMX_SC_R_DBLOGIC = 522,
|
||||
IMX_SC_R_HDMI_PLL_1 = 523,
|
||||
IMX_SC_R_BOARD_R0 = 524,
|
||||
IMX_SC_R_BOARD_R1 = 525,
|
||||
IMX_SC_R_BOARD_R2 = 526,
|
||||
IMX_SC_R_BOARD_R3 = 527,
|
||||
IMX_SC_R_BOARD_R4 = 528,
|
||||
IMX_SC_R_BOARD_R5 = 529,
|
||||
IMX_SC_R_BOARD_R6 = 530,
|
||||
IMX_SC_R_BOARD_R7 = 531,
|
||||
IMX_SC_R_MJPEG_DEC_MP = 532,
|
||||
IMX_SC_R_MJPEG_ENC_MP = 533,
|
||||
IMX_SC_R_VPU_TS_0 = 534,
|
||||
IMX_SC_R_VPU_MU_0 = 535,
|
||||
IMX_SC_R_VPU_MU_1 = 536,
|
||||
IMX_SC_R_VPU_MU_2 = 537,
|
||||
IMX_SC_R_VPU_MU_3 = 538,
|
||||
IMX_SC_R_VPU_ENC_1 = 539,
|
||||
IMX_SC_R_VPU = 540,
|
||||
IMX_SC_R_LAST
|
||||
};
|
||||
|
||||
/* NOTE - please add by replacing some of the UNUSED from above! */
|
||||
|
||||
/*
|
||||
* This type is used to indicate a control.
|
||||
*/
|
||||
enum imx_sc_ctrl {
|
||||
IMX_SC_C_TEMP = 0,
|
||||
IMX_SC_C_TEMP_HI = 1,
|
||||
IMX_SC_C_TEMP_LOW = 2,
|
||||
IMX_SC_C_PXL_LINK_MST1_ADDR = 3,
|
||||
IMX_SC_C_PXL_LINK_MST2_ADDR = 4,
|
||||
IMX_SC_C_PXL_LINK_MST_ENB = 5,
|
||||
IMX_SC_C_PXL_LINK_MST1_ENB = 6,
|
||||
IMX_SC_C_PXL_LINK_MST2_ENB = 7,
|
||||
IMX_SC_C_PXL_LINK_SLV1_ADDR = 8,
|
||||
IMX_SC_C_PXL_LINK_SLV2_ADDR = 9,
|
||||
IMX_SC_C_PXL_LINK_MST_VLD = 10,
|
||||
IMX_SC_C_PXL_LINK_MST1_VLD = 11,
|
||||
IMX_SC_C_PXL_LINK_MST2_VLD = 12,
|
||||
IMX_SC_C_SINGLE_MODE = 13,
|
||||
IMX_SC_C_ID = 14,
|
||||
IMX_SC_C_PXL_CLK_POLARITY = 15,
|
||||
IMX_SC_C_LINESTATE = 16,
|
||||
IMX_SC_C_PCIE_G_RST = 17,
|
||||
IMX_SC_C_PCIE_BUTTON_RST = 18,
|
||||
IMX_SC_C_PCIE_PERST = 19,
|
||||
IMX_SC_C_PHY_RESET = 20,
|
||||
IMX_SC_C_PXL_LINK_RATE_CORRECTION = 21,
|
||||
IMX_SC_C_PANIC = 22,
|
||||
IMX_SC_C_PRIORITY_GROUP = 23,
|
||||
IMX_SC_C_TXCLK = 24,
|
||||
IMX_SC_C_CLKDIV = 25,
|
||||
IMX_SC_C_DISABLE_50 = 26,
|
||||
IMX_SC_C_DISABLE_125 = 27,
|
||||
IMX_SC_C_SEL_125 = 28,
|
||||
IMX_SC_C_MODE = 29,
|
||||
IMX_SC_C_SYNC_CTRL0 = 30,
|
||||
IMX_SC_C_KACHUNK_CNT = 31,
|
||||
IMX_SC_C_KACHUNK_SEL = 32,
|
||||
IMX_SC_C_SYNC_CTRL1 = 33,
|
||||
IMX_SC_C_DPI_RESET = 34,
|
||||
IMX_SC_C_MIPI_RESET = 35,
|
||||
IMX_SC_C_DUAL_MODE = 36,
|
||||
IMX_SC_C_VOLTAGE = 37,
|
||||
IMX_SC_C_PXL_LINK_SEL = 38,
|
||||
IMX_SC_C_OFS_SEL = 39,
|
||||
IMX_SC_C_OFS_AUDIO = 40,
|
||||
IMX_SC_C_OFS_PERIPH = 41,
|
||||
IMX_SC_C_OFS_IRQ = 42,
|
||||
IMX_SC_C_RST0 = 43,
|
||||
IMX_SC_C_RST1 = 44,
|
||||
IMX_SC_C_SEL0 = 45,
|
||||
IMX_SC_C_LAST
|
||||
};
|
||||
|
||||
#endif /* _SC_TYPES_H */
|
||||
Loading…
Reference in New Issue