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arm64: dts: X-Gene: Do not reset or enable/disable clock for AHB block 

Remove register information used to reset and enable/disable clock
for AHB block as reseting AHB or disabling its clock will make other
peripherals attached to it stop working.

Signed-off-by: Duc Dang <dhdang@apm.com>
hifive-unleashed-5.1
Duc Dang 2015-10-22 18:54:57 -07:00
parent 0ae8c00021
commit b0e7a85a97
2 changed files with 6 additions and 16 deletions
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11
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
View File

@ -140,17 +140,12 @@
clock-output-names = "socplldiv2";
};
ahbclk: ahbclk@1f2ac000 {
ahbclk: ahbclk@17000000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f2ac000 0x0 0x1000
0x0 0x17000000 0x0 0x2000>;
reg-names = "csr-reg", "div-reg";
csr-offset = <0x0>;
csr-mask = <0x1>;
enable-offset = <0x8>;
enable-mask = <0x1>;
reg = <0x0 0x17000000 0x0 0x2000>;
reg-names = "div-reg";
divider-offset = <0x164>;
divider-width = <0x5>;
divider-shift = <0x0>;

11
arch/arm64/boot/dts/apm/apm-storm.dtsi
View File

@ -150,17 +150,12 @@
clock-output-names = "socplldiv2";
};
ahbclk: ahbclk@1f2ac000 {
ahbclk: ahbclk@17000000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f2ac000 0x0 0x1000
0x0 0x17000000 0x0 0x2000>;
reg-names = "csr-reg", "div-reg";
csr-offset = <0x0>;
csr-mask = <0x1>;
enable-offset = <0x8>;
enable-mask = <0x1>;
reg = <0x0 0x17000000 0x0 0x2000>;
reg-names = "div-reg";
divider-offset = <0x164>;
divider-width = <0x5>;
divider-shift = <0x0>;