perfcounters: IRQ and NMI support on AMD CPUs
The below completes the K7+ performance counter support: - IRQ support - NMI support KernelTop output works now as well. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Jaswinder Singh Rajput <jaswinder@kernel.org> Cc: Paul Mackerras <paulus@samba.org> LKML-Reference: <1236273633.5187.286.camel@laptop> Signed-off-by: Ingo Molnar <mingo@elte.hu>hifive-unleashed-5.1
Peter Zijlstra
Ingo Molnar
parent
2485e51844
commit
b0f3f28e0f
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@ -28,6 +28,7 @@ static bool perf_counters_initialized __read_mostly;
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static int nr_counters_generic __read_mostly;
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static u64 perf_counter_mask __read_mostly;
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static u64 counter_value_mask __read_mostly;
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static int counter_value_bits __read_mostly;
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static int nr_counters_fixed __read_mostly;
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@ -35,7 +36,9 @@ struct cpu_hw_counters {
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struct perf_counter *counters[X86_PMC_IDX_MAX];
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unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
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unsigned long interrupts;
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u64 global_enable;
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u64 throttle_ctrl;
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u64 active_mask;
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int enabled;
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};
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/*
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@ -43,21 +46,28 @@ struct cpu_hw_counters {
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*/
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struct pmc_x86_ops {
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u64 (*save_disable_all)(void);
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void (*restore_all)(u64 ctrl);
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void (*restore_all)(u64);
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u64 (*get_status)(u64);
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void (*ack_status)(u64);
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void (*enable)(int, u64);
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void (*disable)(int, u64);
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unsigned eventsel;
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unsigned perfctr;
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int (*event_map)(int event);
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u64 (*event_map)(int);
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u64 (*raw_event)(u64);
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int max_events;
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};
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static struct pmc_x86_ops *pmc_ops;
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static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters);
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static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = {
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.enabled = 1,
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};
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/*
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* Intel PerfMon v3. Used on Core2 and later.
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*/
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static const int intel_perfmon_event_map[] =
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static const u64 intel_perfmon_event_map[] =
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{
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[PERF_COUNT_CPU_CYCLES] = 0x003c,
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[PERF_COUNT_INSTRUCTIONS] = 0x00c0,
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@ -68,15 +78,29 @@ static const int intel_perfmon_event_map[] =
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[PERF_COUNT_BUS_CYCLES] = 0x013c,
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};
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static int pmc_intel_event_map(int event)
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static u64 pmc_intel_event_map(int event)
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{
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return intel_perfmon_event_map[event];
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}
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static u64 pmc_intel_raw_event(u64 event)
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{
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#define CORE_EVNTSEL_EVENT_MASK 0x000000FF
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#define CORE_EVNTSEL_UNIT_MASK 0x0000FF00
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#define CORE_EVNTSEL_COUNTER_MASK 0xFF000000
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#define CORE_EVNTSEL_MASK \
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(CORE_EVNTSEL_EVENT_MASK | \
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CORE_EVNTSEL_UNIT_MASK | \
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CORE_EVNTSEL_COUNTER_MASK)
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return event & CORE_EVNTSEL_MASK;
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}
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/*
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* AMD Performance Monitor K7 and later.
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*/
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static const int amd_perfmon_event_map[] =
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static const u64 amd_perfmon_event_map[] =
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{
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[PERF_COUNT_CPU_CYCLES] = 0x0076,
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[PERF_COUNT_INSTRUCTIONS] = 0x00c0,
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@ -86,11 +110,25 @@ static const int amd_perfmon_event_map[] =
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[PERF_COUNT_BRANCH_MISSES] = 0x00c5,
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};
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static int pmc_amd_event_map(int event)
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static u64 pmc_amd_event_map(int event)
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{
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return amd_perfmon_event_map[event];
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}
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static u64 pmc_amd_raw_event(u64 event)
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{
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#define K7_EVNTSEL_EVENT_MASK 0x7000000FF
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#define K7_EVNTSEL_UNIT_MASK 0x00000FF00
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#define K7_EVNTSEL_COUNTER_MASK 0x0FF000000
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#define K7_EVNTSEL_MASK \
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(K7_EVNTSEL_EVENT_MASK | \
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K7_EVNTSEL_UNIT_MASK | \
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K7_EVNTSEL_COUNTER_MASK)
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return event & K7_EVNTSEL_MASK;
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}
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/*
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* Propagate counter elapsed time into the generic counter.
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* Can only be executed on the CPU where the counter is active.
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@ -179,7 +217,7 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
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* Raw event type provide the config in the event structure
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*/
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if (hw_event->raw) {
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hwc->config |= hw_event->type;
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hwc->config |= pmc_ops->raw_event(hw_event->type);
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} else {
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if (hw_event->type >= pmc_ops->max_events)
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return -EINVAL;
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@ -205,18 +243,24 @@ static u64 pmc_intel_save_disable_all(void)
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static u64 pmc_amd_save_disable_all(void)
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{
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int idx;
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u64 val, ctrl = 0;
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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int enabled, idx;
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enabled = cpuc->enabled;
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cpuc->enabled = 0;
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barrier();
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for (idx = 0; idx < nr_counters_generic; idx++) {
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u64 val;
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rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
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if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
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ctrl |= (1 << idx);
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val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
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if (val & ARCH_PERFMON_EVENTSEL0_ENABLE) {
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val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
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}
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}
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return ctrl;
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return enabled;
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}
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u64 hw_perf_save_disable(void)
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@ -226,6 +270,9 @@ u64 hw_perf_save_disable(void)
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return pmc_ops->save_disable_all();
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}
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/*
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* Exported because of ACPI idle
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*/
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EXPORT_SYMBOL_GPL(hw_perf_save_disable);
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static void pmc_intel_restore_all(u64 ctrl)
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@ -235,11 +282,18 @@ static void pmc_intel_restore_all(u64 ctrl)
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static void pmc_amd_restore_all(u64 ctrl)
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{
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u64 val;
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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int idx;
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cpuc->enabled = ctrl;
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barrier();
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if (!ctrl)
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return;
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for (idx = 0; idx < nr_counters_generic; idx++) {
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if (ctrl & (1 << idx)) {
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if (test_bit(idx, (unsigned long *)&cpuc->active_mask)) {
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u64 val;
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rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
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val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
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@ -254,8 +308,112 @@ void hw_perf_restore(u64 ctrl)
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pmc_ops->restore_all(ctrl);
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}
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/*
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* Exported because of ACPI idle
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*/
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EXPORT_SYMBOL_GPL(hw_perf_restore);
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static u64 pmc_intel_get_status(u64 mask)
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{
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u64 status;
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rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
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return status;
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}
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static u64 pmc_amd_get_status(u64 mask)
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{
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u64 status = 0;
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int idx;
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for (idx = 0; idx < nr_counters_generic; idx++) {
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s64 val;
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if (!(mask & (1 << idx)))
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continue;
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rdmsrl(MSR_K7_PERFCTR0 + idx, val);
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val <<= (64 - counter_value_bits);
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if (val >= 0)
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status |= (1 << idx);
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}
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return status;
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}
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static u64 hw_perf_get_status(u64 mask)
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{
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if (unlikely(!perf_counters_initialized))
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return 0;
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return pmc_ops->get_status(mask);
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}
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static void pmc_intel_ack_status(u64 ack)
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{
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wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
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}
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static void pmc_amd_ack_status(u64 ack)
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{
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}
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static void hw_perf_ack_status(u64 ack)
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{
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if (unlikely(!perf_counters_initialized))
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return;
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pmc_ops->ack_status(ack);
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}
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static void pmc_intel_enable(int idx, u64 config)
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{
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wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx,
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config | ARCH_PERFMON_EVENTSEL0_ENABLE);
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}
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static void pmc_amd_enable(int idx, u64 config)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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set_bit(idx, (unsigned long *)&cpuc->active_mask);
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if (cpuc->enabled)
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config |= ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsrl(MSR_K7_EVNTSEL0 + idx, config);
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}
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static void hw_perf_enable(int idx, u64 config)
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{
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if (unlikely(!perf_counters_initialized))
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return;
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pmc_ops->enable(idx, config);
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}
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static void pmc_intel_disable(int idx, u64 config)
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{
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wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, config);
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}
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static void pmc_amd_disable(int idx, u64 config)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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clear_bit(idx, (unsigned long *)&cpuc->active_mask);
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wrmsrl(MSR_K7_EVNTSEL0 + idx, config);
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}
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static void hw_perf_disable(int idx, u64 config)
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{
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if (unlikely(!perf_counters_initialized))
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return;
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pmc_ops->disable(idx, config);
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}
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static inline void
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__pmc_fixed_disable(struct perf_counter *counter,
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struct hw_perf_counter *hwc, unsigned int __idx)
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@ -278,7 +436,7 @@ __pmc_generic_disable(struct perf_counter *counter,
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if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL))
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__pmc_fixed_disable(counter, hwc, idx);
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else
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wrmsr_safe(hwc->config_base + idx, hwc->config, 0);
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hw_perf_disable(idx, hwc->config);
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}
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static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]);
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@ -354,8 +512,7 @@ __pmc_generic_enable(struct perf_counter *counter,
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if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL))
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__pmc_fixed_enable(counter, hwc, idx);
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else
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wrmsr(hwc->config_base + idx,
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hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE, 0);
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hw_perf_enable(idx, hwc->config);
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}
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static int
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@ -567,22 +724,20 @@ perf_handle_group(struct perf_counter *sibling, u64 *status, u64 *overflown)
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* This handler is triggered by the local APIC, so the APIC IRQ handling
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* rules apply:
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*/
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static void __smp_perf_counter_interrupt(struct pt_regs *regs, int nmi)
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static int __smp_perf_counter_interrupt(struct pt_regs *regs, int nmi)
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{
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int bit, cpu = smp_processor_id();
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u64 ack, status;
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struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu);
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int ret = 0;
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rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, cpuc->global_enable);
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cpuc->throttle_ctrl = hw_perf_save_disable();
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/* Disable counters globally */
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wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
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ack_APIC_irq();
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rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
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status = hw_perf_get_status(cpuc->throttle_ctrl);
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if (!status)
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goto out;
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ret = 1;
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again:
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inc_irq_stat(apic_perf_irqs);
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ack = status;
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@ -618,12 +773,12 @@ again:
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}
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}
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wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
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hw_perf_ack_status(ack);
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/*
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* Repeat if there is more work to be done:
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*/
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rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
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status = hw_perf_get_status(cpuc->throttle_ctrl);
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if (status)
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goto again;
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out:
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@ -631,32 +786,27 @@ out:
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* Restore - do not reenable when global enable is off or throttled:
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*/
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if (++cpuc->interrupts < PERFMON_MAX_INTERRUPTS)
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wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, cpuc->global_enable);
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hw_perf_restore(cpuc->throttle_ctrl);
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return ret;
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}
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void perf_counter_unthrottle(void)
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{
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struct cpu_hw_counters *cpuc;
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u64 global_enable;
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if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
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return;
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
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return;
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if (unlikely(!perf_counters_initialized))
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return;
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cpuc = &per_cpu(cpu_hw_counters, smp_processor_id());
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cpuc = &__get_cpu_var(cpu_hw_counters);
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if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) {
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if (printk_ratelimit())
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printk(KERN_WARNING "PERFMON: max interrupts exceeded!\n");
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wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, cpuc->global_enable);
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hw_perf_restore(cpuc->throttle_ctrl);
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}
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rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, global_enable);
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if (unlikely(cpuc->global_enable && !global_enable))
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wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, cpuc->global_enable);
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cpuc->interrupts = 0;
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}
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@ -664,8 +814,8 @@ void smp_perf_counter_interrupt(struct pt_regs *regs)
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{
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irq_enter();
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apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
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ack_APIC_irq();
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__smp_perf_counter_interrupt(regs, 0);
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irq_exit();
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}
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@ -722,16 +872,23 @@ perf_counter_nmi_handler(struct notifier_block *self,
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{
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struct die_args *args = __args;
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struct pt_regs *regs;
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int ret;
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if (likely(cmd != DIE_NMI_IPI))
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switch (cmd) {
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case DIE_NMI:
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case DIE_NMI_IPI:
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break;
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default:
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return NOTIFY_DONE;
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}
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regs = args->regs;
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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__smp_perf_counter_interrupt(regs, 1);
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ret = __smp_perf_counter_interrupt(regs, 1);
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return NOTIFY_STOP;
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return ret ? NOTIFY_STOP : NOTIFY_OK;
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}
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static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
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@ -743,18 +900,28 @@ static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
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static struct pmc_x86_ops pmc_intel_ops = {
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.save_disable_all = pmc_intel_save_disable_all,
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.restore_all = pmc_intel_restore_all,
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.get_status = pmc_intel_get_status,
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.ack_status = pmc_intel_ack_status,
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.enable = pmc_intel_enable,
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.disable = pmc_intel_disable,
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.eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
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.perfctr = MSR_ARCH_PERFMON_PERFCTR0,
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.event_map = pmc_intel_event_map,
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.raw_event = pmc_intel_raw_event,
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.max_events = ARRAY_SIZE(intel_perfmon_event_map),
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};
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static struct pmc_x86_ops pmc_amd_ops = {
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.save_disable_all = pmc_amd_save_disable_all,
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.restore_all = pmc_amd_restore_all,
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.get_status = pmc_amd_get_status,
|
||||
.ack_status = pmc_amd_ack_status,
|
||||
.enable = pmc_amd_enable,
|
||||
.disable = pmc_amd_disable,
|
||||
.eventsel = MSR_K7_EVNTSEL0,
|
||||
.perfctr = MSR_K7_PERFCTR0,
|
||||
.event_map = pmc_amd_event_map,
|
||||
.raw_event = pmc_amd_raw_event,
|
||||
.max_events = ARRAY_SIZE(amd_perfmon_event_map),
|
||||
};
|
||||
|
||||
|
|
@ -787,8 +954,25 @@ static struct pmc_x86_ops *pmc_intel_init(void)
|
|||
|
||||
static struct pmc_x86_ops *pmc_amd_init(void)
|
||||
{
|
||||
u64 old;
|
||||
int bits;
|
||||
|
||||
nr_counters_generic = 4;
|
||||
nr_counters_fixed = 0;
|
||||
counter_value_mask = ~0ULL;
|
||||
|
||||
rdmsrl(MSR_K7_PERFCTR0, old);
|
||||
wrmsrl(MSR_K7_PERFCTR0, counter_value_mask);
|
||||
/*
|
||||
* read the truncated mask
|
||||
*/
|
||||
rdmsrl(MSR_K7_PERFCTR0, counter_value_mask);
|
||||
wrmsrl(MSR_K7_PERFCTR0, old);
|
||||
|
||||
bits = 32 + fls(counter_value_mask >> 32);
|
||||
if (bits == 32)
|
||||
bits = fls((u32)counter_value_mask);
|
||||
counter_value_bits = bits;
|
||||
|
||||
pr_info("AMD Performance Monitoring support detected.\n");
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue