drm/i915/fbc: introduce struct intel_fbc_reg_params
The early return inside __intel_fbc_update does not completely check all the parameters that affect the FBC register values. For example, we currently lack looking at crtc->adjusted_y (for the fence Y offset) and all the parameters that affect the CFB size (for i8xx). Instead of just adding the missing parameters to the check and hoping that any changes to the fbc_activate functions also come with a matching change to the __intel_fbc_update check, introduce a new structure where we store these parameters and use the structure at the fbc_activate function. Of course, it's still possible to access everything from dev_priv in those functions, but IMHO the new code will be harder to break. v2: Rebase. Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1453210558-7875-5-git-send-email-paulo.r.zanoni@intel.com
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@ -905,11 +905,9 @@ struct i915_fbc {
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* it's the outer lock when overlapping with stolen_lock. */
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struct mutex lock;
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unsigned threshold;
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unsigned int fb_id;
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unsigned int possible_framebuffer_bits;
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unsigned int busy_bits;
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struct intel_crtc *crtc;
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int y;
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struct drm_mm_node compressed_fb;
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struct drm_mm_node *compressed_llb;
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@ -919,6 +917,24 @@ struct i915_fbc {
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bool enabled;
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bool active;
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struct intel_fbc_reg_params {
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struct {
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enum pipe pipe;
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enum plane plane;
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unsigned int fence_y_offset;
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} crtc;
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struct {
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u64 ggtt_offset;
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uint32_t id;
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uint32_t pixel_format;
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unsigned int stride;
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int fence_reg;
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} fb;
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int cfb_size;
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} params;
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struct intel_fbc_work {
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bool scheduled;
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u32 scheduled_vblank;
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@ -929,7 +945,7 @@ struct i915_fbc {
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const char *no_fbc_reason;
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bool (*is_active)(struct drm_i915_private *dev_priv);
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void (*activate)(struct intel_crtc *crtc);
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void (*activate)(struct drm_i915_private *dev_priv);
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void (*deactivate)(struct drm_i915_private *dev_priv);
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};
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@ -130,11 +130,9 @@ static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
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}
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}
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static void i8xx_fbc_activate(struct intel_crtc *crtc)
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static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
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struct drm_framebuffer *fb = crtc->base.primary->fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
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int cfb_pitch;
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int i;
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u32 fbc_ctl;
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@ -142,9 +140,9 @@ static void i8xx_fbc_activate(struct intel_crtc *crtc)
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dev_priv->fbc.active = true;
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/* Note: fbc.threshold == 1 for i8xx */
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cfb_pitch = intel_fbc_calculate_cfb_size(crtc, fb) / FBC_LL_SIZE;
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if (fb->pitches[0] < cfb_pitch)
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cfb_pitch = fb->pitches[0];
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cfb_pitch = params->cfb_size / FBC_LL_SIZE;
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if (params->fb.stride < cfb_pitch)
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cfb_pitch = params->fb.stride;
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/* FBC_CTL wants 32B or 64B units */
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if (IS_GEN2(dev_priv))
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@ -161,9 +159,9 @@ static void i8xx_fbc_activate(struct intel_crtc *crtc)
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/* Set it up... */
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fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
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fbc_ctl2 |= FBC_CTL_PLANE(crtc->plane);
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fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane);
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I915_WRITE(FBC_CONTROL2, fbc_ctl2);
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I915_WRITE(FBC_FENCE_OFF, get_crtc_fence_y_offset(crtc));
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I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
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}
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/* enable it... */
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@ -173,7 +171,7 @@ static void i8xx_fbc_activate(struct intel_crtc *crtc)
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if (IS_I945GM(dev_priv))
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fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
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fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
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fbc_ctl |= obj->fence_reg;
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fbc_ctl |= params->fb.fence_reg;
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I915_WRITE(FBC_CONTROL, fbc_ctl);
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}
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@ -182,23 +180,21 @@ static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
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return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
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}
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static void g4x_fbc_activate(struct intel_crtc *crtc)
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static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
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struct drm_framebuffer *fb = crtc->base.primary->fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
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u32 dpfc_ctl;
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dev_priv->fbc.active = true;
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dpfc_ctl = DPFC_CTL_PLANE(crtc->plane) | DPFC_SR_EN;
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if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
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dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN;
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if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
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dpfc_ctl |= DPFC_CTL_LIMIT_2X;
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else
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dpfc_ctl |= DPFC_CTL_LIMIT_1X;
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dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
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dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fb.fence_reg;
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I915_WRITE(DPFC_FENCE_YOFF, get_crtc_fence_y_offset(crtc));
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I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
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/* enable it... */
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I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
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@ -230,19 +226,16 @@ static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
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POSTING_READ(MSG_FBC_REND_STATE);
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}
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static void ilk_fbc_activate(struct intel_crtc *crtc)
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static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
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struct drm_framebuffer *fb = crtc->base.primary->fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
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u32 dpfc_ctl;
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int threshold = dev_priv->fbc.threshold;
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unsigned int y_offset;
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dev_priv->fbc.active = true;
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dpfc_ctl = DPFC_CTL_PLANE(crtc->plane);
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if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
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dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane);
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if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
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threshold++;
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switch (threshold) {
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@ -259,18 +252,17 @@ static void ilk_fbc_activate(struct intel_crtc *crtc)
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}
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dpfc_ctl |= DPFC_CTL_FENCE_EN;
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if (IS_GEN5(dev_priv))
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dpfc_ctl |= obj->fence_reg;
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dpfc_ctl |= params->fb.fence_reg;
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y_offset = get_crtc_fence_y_offset(crtc);
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I915_WRITE(ILK_DPFC_FENCE_YOFF, y_offset);
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I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
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I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
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I915_WRITE(ILK_FBC_RT_BASE, params->fb.ggtt_offset | ILK_FBC_RT_VALID);
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/* enable it... */
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I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
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if (IS_GEN6(dev_priv)) {
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I915_WRITE(SNB_DPFC_CTL_SA,
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SNB_CPU_FENCE_ENABLE | obj->fence_reg);
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I915_WRITE(DPFC_CPU_FENCE_OFFSET, y_offset);
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SNB_CPU_FENCE_ENABLE | params->fb.fence_reg);
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I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
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}
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intel_fbc_recompress(dev_priv);
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@ -295,11 +287,9 @@ static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
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return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
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}
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static void gen7_fbc_activate(struct intel_crtc *crtc)
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static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
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struct drm_framebuffer *fb = crtc->base.primary->fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
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u32 dpfc_ctl;
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int threshold = dev_priv->fbc.threshold;
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dpfc_ctl = 0;
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if (IS_IVYBRIDGE(dev_priv))
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dpfc_ctl |= IVB_DPFC_CTL_PLANE(crtc->plane);
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dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
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if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
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if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
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threshold++;
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switch (threshold) {
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ILK_FBCQ_DIS);
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} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
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/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
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I915_WRITE(CHICKEN_PIPESL_1(crtc->pipe),
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I915_READ(CHICKEN_PIPESL_1(crtc->pipe)) |
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I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
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I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
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HSW_FBCQ_DIS);
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}
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I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
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I915_WRITE(SNB_DPFC_CTL_SA,
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SNB_CPU_FENCE_ENABLE | obj->fence_reg);
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I915_WRITE(DPFC_CPU_FENCE_OFFSET, get_crtc_fence_y_offset(crtc));
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SNB_CPU_FENCE_ENABLE | params->fb.fence_reg);
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I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
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intel_fbc_recompress(dev_priv);
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}
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@ -364,17 +354,6 @@ bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
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return dev_priv->fbc.active;
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}
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static void intel_fbc_activate(const struct drm_framebuffer *fb)
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{
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struct drm_i915_private *dev_priv = fb->dev->dev_private;
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struct intel_crtc *crtc = dev_priv->fbc.crtc;
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dev_priv->fbc.activate(crtc);
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dev_priv->fbc.fb_id = fb->base.id;
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dev_priv->fbc.y = crtc->base.y;
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}
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static void intel_fbc_work_fn(struct work_struct *__work)
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{
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struct drm_i915_private *dev_priv =
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}
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if (crtc->base.primary->fb == work->fb)
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intel_fbc_activate(work->fb);
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dev_priv->fbc.activate(dev_priv);
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work->scheduled = false;
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return true;
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}
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static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
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struct intel_fbc_reg_params *params)
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{
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struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
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struct drm_framebuffer *fb = crtc->base.primary->fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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/* Since all our fields are integer types, use memset here so the
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* comparison function can rely on memcmp because the padding will be
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* zero. */
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memset(params, 0, sizeof(*params));
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params->crtc.pipe = crtc->pipe;
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params->crtc.plane = crtc->plane;
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params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
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params->fb.id = fb->base.id;
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params->fb.pixel_format = fb->pixel_format;
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params->fb.stride = fb->pitches[0];
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params->fb.fence_reg = obj->fence_reg;
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params->cfb_size = intel_fbc_calculate_cfb_size(crtc, fb);
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/* FIXME: We lack the proper locking here, so only run this on the
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* platforms that need. */
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if (dev_priv->fbc.activate == ilk_fbc_activate)
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params->fb.ggtt_offset = i915_gem_obj_ggtt_offset(obj);
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}
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static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
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struct intel_fbc_reg_params *params2)
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{
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/* We can use this since intel_fbc_get_reg_params() does a memset. */
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return memcmp(params1, params2, sizeof(*params1)) == 0;
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}
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/**
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* __intel_fbc_update - activate/deactivate FBC as needed, unlocked
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* @crtc: the CRTC that triggered the update
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static void __intel_fbc_update(struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
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struct intel_fbc_reg_params old_params;
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WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock));
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if (!intel_fbc_can_activate(crtc))
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goto out_disable;
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old_params = dev_priv->fbc.params;
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intel_fbc_get_reg_params(crtc, &dev_priv->fbc.params);
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/* If the scanout has not changed, don't modify the FBC settings.
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* Note that we make the fundamental assumption that the fb->obj
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* cannot be unpinned (and have its GTT offset and fence revoked)
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* without first being decoupled from the scanout and FBC disabled.
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*/
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if (dev_priv->fbc.crtc == crtc &&
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dev_priv->fbc.fb_id == crtc->base.primary->fb->base.id &&
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dev_priv->fbc.y == crtc->base.y &&
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dev_priv->fbc.active)
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if (dev_priv->fbc.active &&
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intel_fbc_reg_params_equal(&old_params, &dev_priv->fbc.params))
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return;
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if (intel_fbc_is_active(dev_priv)) {
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