Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/radeon/kms: fix segfault in pm rework drm/radeon/kms: fix up gpio i2c mask bits for r4xx drm/radeon: add some missing FireMV pci ids vgaarb: a NULL bridge is acceptable for root devices. drm: Remove utterly bogus preempt_disable() sections
This commit is contained in:
commit
b1914cb2f3
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@ -110,10 +110,7 @@ static void vblank_disable_and_save(struct drm_device *dev, int crtc)
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/* Prevent vblank irq processing while disabling vblank irqs,
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/* Prevent vblank irq processing while disabling vblank irqs,
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* so no updates of timestamps or count can happen after we've
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* so no updates of timestamps or count can happen after we've
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* disabled. Needed to prevent races in case of delayed irq's.
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* disabled. Needed to prevent races in case of delayed irq's.
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* Disable preemption, so vblank_time_lock is held as short as
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* possible, even under a kernel with PREEMPT_RT patches.
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*/
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*/
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preempt_disable();
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spin_lock_irqsave(&dev->vblank_time_lock, irqflags);
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spin_lock_irqsave(&dev->vblank_time_lock, irqflags);
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dev->driver->disable_vblank(dev, crtc);
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dev->driver->disable_vblank(dev, crtc);
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@ -164,7 +161,6 @@ static void vblank_disable_and_save(struct drm_device *dev, int crtc)
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clear_vblank_timestamps(dev, crtc);
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clear_vblank_timestamps(dev, crtc);
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spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
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spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
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preempt_enable();
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}
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}
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static void vblank_disable_fn(unsigned long arg)
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static void vblank_disable_fn(unsigned long arg)
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@ -889,10 +885,6 @@ int drm_vblank_get(struct drm_device *dev, int crtc)
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spin_lock_irqsave(&dev->vbl_lock, irqflags);
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spin_lock_irqsave(&dev->vbl_lock, irqflags);
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/* Going from 0->1 means we have to enable interrupts again */
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/* Going from 0->1 means we have to enable interrupts again */
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if (atomic_add_return(1, &dev->vblank_refcount[crtc]) == 1) {
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if (atomic_add_return(1, &dev->vblank_refcount[crtc]) == 1) {
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/* Disable preemption while holding vblank_time_lock. Do
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* it explicitely to guard against PREEMPT_RT kernel.
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*/
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preempt_disable();
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spin_lock_irqsave(&dev->vblank_time_lock, irqflags2);
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spin_lock_irqsave(&dev->vblank_time_lock, irqflags2);
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if (!dev->vblank_enabled[crtc]) {
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if (!dev->vblank_enabled[crtc]) {
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/* Enable vblank irqs under vblank_time_lock protection.
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/* Enable vblank irqs under vblank_time_lock protection.
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@ -912,7 +904,6 @@ int drm_vblank_get(struct drm_device *dev, int crtc)
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}
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}
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}
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}
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spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags2);
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spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags2);
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preempt_enable();
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} else {
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} else {
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if (!dev->vblank_enabled[crtc]) {
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if (!dev->vblank_enabled[crtc]) {
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atomic_dec(&dev->vblank_refcount[crtc]);
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atomic_dec(&dev->vblank_refcount[crtc]);
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@ -85,6 +85,18 @@ static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rd
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for (i = 0; i < num_indices; i++) {
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for (i = 0; i < num_indices; i++) {
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gpio = &i2c_info->asGPIO_Info[i];
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gpio = &i2c_info->asGPIO_Info[i];
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/* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
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if ((rdev->family == CHIP_R420) ||
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(rdev->family == CHIP_R423) ||
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(rdev->family == CHIP_RV410)) {
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if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
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(le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
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(le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
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gpio->ucClkMaskShift = 0x19;
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gpio->ucDataMaskShift = 0x18;
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}
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}
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/* some evergreen boards have bad data for this entry */
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/* some evergreen boards have bad data for this entry */
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if (ASIC_IS_DCE4(rdev)) {
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if (ASIC_IS_DCE4(rdev)) {
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if ((i == 7) &&
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if ((i == 7) &&
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@ -1996,14 +2008,14 @@ static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
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return state_index;
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return state_index;
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/* last mode is usually default, array is low to high */
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/* last mode is usually default, array is low to high */
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for (i = 0; i < num_modes; i++) {
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for (i = 0; i < num_modes; i++) {
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rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
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switch (frev) {
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case 1:
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rdev->pm.power_state[state_index].clock_info =
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rdev->pm.power_state[state_index].clock_info =
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kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
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kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
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if (!rdev->pm.power_state[state_index].clock_info)
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if (!rdev->pm.power_state[state_index].clock_info)
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return state_index;
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return state_index;
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rdev->pm.power_state[state_index].num_clock_modes = 1;
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rdev->pm.power_state[state_index].num_clock_modes = 1;
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rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
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switch (frev) {
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case 1:
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rdev->pm.power_state[state_index].clock_info[0].mclk =
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rdev->pm.power_state[state_index].clock_info[0].mclk =
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le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
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le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
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rdev->pm.power_state[state_index].clock_info[0].sclk =
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rdev->pm.power_state[state_index].clock_info[0].sclk =
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@ -2039,11 +2051,6 @@ static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
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state_index++;
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state_index++;
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break;
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break;
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case 2:
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case 2:
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rdev->pm.power_state[state_index].clock_info =
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kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
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if (!rdev->pm.power_state[state_index].clock_info)
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return state_index;
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rdev->pm.power_state[state_index].num_clock_modes = 1;
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rdev->pm.power_state[state_index].clock_info[0].mclk =
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rdev->pm.power_state[state_index].clock_info[0].mclk =
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le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
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le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
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rdev->pm.power_state[state_index].clock_info[0].sclk =
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rdev->pm.power_state[state_index].clock_info[0].sclk =
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@ -2080,11 +2087,6 @@ static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
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state_index++;
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state_index++;
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break;
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break;
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case 3:
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case 3:
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rdev->pm.power_state[state_index].clock_info =
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kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
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if (!rdev->pm.power_state[state_index].clock_info)
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return state_index;
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rdev->pm.power_state[state_index].num_clock_modes = 1;
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rdev->pm.power_state[state_index].clock_info[0].mclk =
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rdev->pm.power_state[state_index].clock_info[0].mclk =
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le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
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le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
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rdev->pm.power_state[state_index].clock_info[0].sclk =
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rdev->pm.power_state[state_index].clock_info[0].sclk =
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@ -465,7 +465,6 @@ static void vga_arbiter_check_bridge_sharing(struct vga_device *vgadev)
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while (new_bus) {
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while (new_bus) {
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new_bridge = new_bus->self;
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new_bridge = new_bus->self;
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if (new_bridge) {
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/* go through list of devices already registered */
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/* go through list of devices already registered */
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list_for_each_entry(same_bridge_vgadev, &vga_list, list) {
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list_for_each_entry(same_bridge_vgadev, &vga_list, list) {
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bus = same_bridge_vgadev->pdev->bus;
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bus = same_bridge_vgadev->pdev->bus;
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@ -491,7 +490,6 @@ static void vga_arbiter_check_bridge_sharing(struct vga_device *vgadev)
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bus = bus->parent;
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bus = bus->parent;
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}
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}
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}
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}
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}
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new_bus = new_bus->parent;
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new_bus = new_bus->parent;
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}
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}
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}
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}
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@ -4,6 +4,7 @@
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*/
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*/
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#define radeon_PCI_IDS \
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#define radeon_PCI_IDS \
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{0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
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{0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
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{0x1002, 0x3151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x3152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x3152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x3154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x3154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x3155, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x3155, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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@ -55,6 +56,7 @@
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{0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
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{0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
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{0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
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{0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
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{0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
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{0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
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{0x1002, 0x4C6E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
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{0x1002, 0x4E44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
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{0x1002, 0x4E44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
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{0x1002, 0x4E45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
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{0x1002, 0x4E45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
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{0x1002, 0x4E46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
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{0x1002, 0x4E46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
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