x86/fpu: Reorganize fpu/internal.h
fpu/internal.h has grown organically, with not much high level structure, which hurts its readability. Organize the various definitions into 5 sections: - high level FPU state functions - FPU/CPU feature flag helpers - fpstate handling functions - FPU context switching helpers - misc helper functions Other related changes: - Move MXCSR_DEFAULT to fpu/types.h. - drop the unused X87_FSW_ES define No change in functionality. Cc: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org>hifive-unleashed-5.1
Ingo Molnar
parent
e97131a839
commit
b1b64dc355
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@ -18,32 +18,6 @@
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#include <asm/fpu/api.h>
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#include <asm/fpu/xstate.h>
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#define MXCSR_DEFAULT 0x1f80
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extern unsigned int mxcsr_feature_mask;
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extern union fpregs_state init_fpstate;
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extern void fpu__init_cpu(void);
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extern void fpu__init_system_xstate(void);
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extern void fpu__init_cpu_xstate(void);
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extern void fpu__init_system(struct cpuinfo_x86 *c);
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extern void fpstate_init(union fpregs_state *state);
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#ifdef CONFIG_MATH_EMULATION
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extern void fpstate_init_soft(struct swregs_state *soft);
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#else
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static inline void fpstate_init_soft(struct swregs_state *soft) {}
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#endif
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static inline void fpstate_init_fxstate(struct fxregs_state *fx)
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{
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fx->cwd = 0x37f;
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fx->mxcsr = MXCSR_DEFAULT;
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}
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extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
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extern int fpu__exception_code(struct fpu *fpu, int trap_nr);
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/*
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* High level FPU state handling functions:
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*/
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@ -55,7 +29,16 @@ extern int fpu__restore_sig(void __user *buf, int ia32_frame);
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extern void fpu__drop(struct fpu *fpu);
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extern int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu);
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extern void fpu__clear(struct fpu *fpu);
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extern int fpu__exception_code(struct fpu *fpu, int trap_nr);
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extern int dump_fpu(struct pt_regs *ptregs, struct user_i387_struct *fpstate);
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/*
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* Boot time FPU initialization functions:
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*/
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extern void fpu__init_cpu(void);
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extern void fpu__init_system_xstate(void);
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extern void fpu__init_cpu_xstate(void);
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extern void fpu__init_system(struct cpuinfo_x86 *c);
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extern void fpu__init_check_bugs(void);
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extern void fpu__resume_cpu(void);
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@ -68,27 +51,9 @@ extern void fpu__resume_cpu(void);
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# define WARN_ON_FPU(x) ({ 0; })
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#endif
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DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
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/*
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* Must be run with preemption disabled: this clears the fpu_fpregs_owner_ctx,
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* on this CPU.
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*
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* This will disable any lazy FPU state restore of the current FPU state,
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* but if the current thread owns the FPU, it will still be saved by.
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* FPU related CPU feature flag helper routines:
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*/
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static inline void __cpu_disable_lazy_restore(unsigned int cpu)
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{
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per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
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}
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static inline int fpu_want_lazy_restore(struct fpu *fpu, unsigned int cpu)
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{
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return fpu == this_cpu_read_stable(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu;
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}
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#define X87_FSW_ES (1 << 7) /* Exception Summary */
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static __always_inline __pure bool use_eager_fpu(void)
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{
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return static_cpu_has_safe(X86_FEATURE_EAGER_FPU);
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@ -109,6 +74,23 @@ static __always_inline __pure bool use_fxsr(void)
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return static_cpu_has_safe(X86_FEATURE_FXSR);
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}
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/*
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* fpstate handling functions:
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*/
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extern union fpregs_state init_fpstate;
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extern void fpstate_init(union fpregs_state *state);
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#ifdef CONFIG_MATH_EMULATION
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extern void fpstate_init_soft(struct swregs_state *soft);
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#else
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static inline void fpstate_init_soft(struct swregs_state *soft) {}
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#endif
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static inline void fpstate_init_fxstate(struct fxregs_state *fx)
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{
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fx->cwd = 0x37f;
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fx->mxcsr = MXCSR_DEFAULT;
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}
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extern void fpstate_sanitize_xstate(struct fpu *fpu);
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#define user_insn(insn, output, input...) \
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@ -285,6 +267,32 @@ static inline int copy_fpstate_to_fpregs(struct fpu *fpu)
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return __copy_fpstate_to_fpregs(fpu);
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}
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extern int copy_fpstate_to_sigframe(void __user *buf, void __user *fx, int size);
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/*
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* FPU context switch related helper methods:
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*/
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DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
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/*
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* Must be run with preemption disabled: this clears the fpu_fpregs_owner_ctx,
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* on this CPU.
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*
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* This will disable any lazy FPU state restore of the current FPU state,
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* but if the current thread owns the FPU, it will still be saved by.
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*/
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static inline void __cpu_disable_lazy_restore(unsigned int cpu)
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{
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per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
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}
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static inline int fpu_want_lazy_restore(struct fpu *fpu, unsigned int cpu)
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{
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return fpu == this_cpu_read_stable(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu;
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}
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/*
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* Wrap lazy FPU TS handling in a 'hw fpregs activation/deactivation'
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* idiom, which is then paired with the sw-flag (fpregs_active) later on:
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@ -354,31 +362,6 @@ static inline void fpregs_deactivate(struct fpu *fpu)
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__fpregs_deactivate_hw();
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}
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/*
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* Definitions for the eXtended Control Register instructions
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*/
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#define XCR_XFEATURE_ENABLED_MASK 0x00000000
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static inline u64 xgetbv(u32 index)
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{
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u32 eax, edx;
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asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */
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: "=a" (eax), "=d" (edx)
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: "c" (index));
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return eax + ((u64)edx << 32);
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}
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static inline void xsetbv(u32 index, u64 value)
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{
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u32 eax = value;
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u32 edx = value >> 32;
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asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */
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: : "a" (eax), "d" (edx), "c" (index));
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}
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/*
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* FPU state switching for scheduling.
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*
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@ -437,6 +420,10 @@ switch_fpu_prepare(struct fpu *old_fpu, struct fpu *new_fpu, int cpu)
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return fpu;
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}
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/*
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* Misc helper functions:
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*/
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/*
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* By the time this gets called, we've already cleared CR0.TS and
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* given the process the FPU if we are going to preload the FPU
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@ -453,11 +440,6 @@ static inline void switch_fpu_finish(struct fpu *new_fpu, fpu_switch_t fpu_switc
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}
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}
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/*
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* Signal frame handlers...
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*/
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extern int copy_fpstate_to_sigframe(void __user *buf, void __user *fx, int size);
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/*
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* Needs to be preemption-safe.
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*
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@ -476,4 +458,31 @@ static inline void user_fpu_begin(void)
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preempt_enable();
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}
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/*
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* MXCSR and XCR definitions:
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*/
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extern unsigned int mxcsr_feature_mask;
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#define XCR_XFEATURE_ENABLED_MASK 0x00000000
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static inline u64 xgetbv(u32 index)
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{
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u32 eax, edx;
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asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */
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: "=a" (eax), "=d" (edx)
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: "c" (index));
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return eax + ((u64)edx << 32);
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}
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static inline void xsetbv(u32 index, u64 value)
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{
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u32 eax = value;
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u32 edx = value >> 32;
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asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */
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: : "a" (eax), "d" (edx), "c" (index));
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}
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#endif /* _ASM_X86_FPU_INTERNAL_H */
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@ -65,6 +65,9 @@ struct fxregs_state {
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} __attribute__((aligned(16)));
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/* Default value for fxregs_state.mxcsr: */
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#define MXCSR_DEFAULT 0x1f80
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/*
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* Software based FPU emulation state. This is arbitrary really,
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* it matches the x87 format to make it easier to understand:
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