scsi: qla2xxx: Flush mailbox commands on chip reset
Flush pending mailbox commands on chip reset. Wake up command that's waiting for an interrupt and wait for mailbox counters to go to zero. Signed-off-by: Quinn Tran <quinn.tran@cavium.com> Signed-off-by: Himanshu Madhani <himanshu.madhani@cavium.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
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cb97f2c2e8
commit
b2000805a9
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@ -3598,6 +3598,7 @@ struct qla_hw_data {
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uint32_t detected_lr_sfp:1;
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uint32_t detected_lr_sfp:1;
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uint32_t using_lr_setting:1;
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uint32_t using_lr_setting:1;
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uint32_t rida_fmt2:1;
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uint32_t rida_fmt2:1;
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uint32_t purge_mbox:1;
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} flags;
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} flags;
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uint16_t max_exchg;
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uint16_t max_exchg;
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@ -3843,6 +3844,9 @@ struct qla_hw_data {
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int port_down_retry_count;
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int port_down_retry_count;
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uint8_t mbx_count;
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uint8_t mbx_count;
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uint8_t aen_mbx_count;
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uint8_t aen_mbx_count;
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atomic_t num_pend_mbx_stage1;
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atomic_t num_pend_mbx_stage2;
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atomic_t num_pend_mbx_stage3;
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uint32_t login_retry_count;
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uint32_t login_retry_count;
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/* SNS command interfaces. */
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/* SNS command interfaces. */
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@ -4156,6 +4160,7 @@ struct qla_hw_data {
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struct work_struct board_disable;
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struct work_struct board_disable;
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struct mr_data_fx00 mr;
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struct mr_data_fx00 mr;
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uint32_t chip_reset;
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struct qlt_hw_data tgt;
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struct qlt_hw_data tgt;
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int allow_cna_fw_dump;
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int allow_cna_fw_dump;
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@ -6283,6 +6283,7 @@ qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
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ql_log(ql_log_info, vha, 0x00af,
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ql_log(ql_log_info, vha, 0x00af,
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"Performing ISP error recovery - ha=%p.\n", ha);
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"Performing ISP error recovery - ha=%p.\n", ha);
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ha->flags.purge_mbox = 1;
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/* For ISP82XX, reset_chip is just disabling interrupts.
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/* For ISP82XX, reset_chip is just disabling interrupts.
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* Driver waits for the completion of the commands.
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* Driver waits for the completion of the commands.
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* the interrupts need to be enabled.
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* the interrupts need to be enabled.
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@ -6297,13 +6298,31 @@ qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
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ha->current_topology = 0;
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ha->current_topology = 0;
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ha->flags.fw_started = 0;
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ha->flags.fw_started = 0;
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ha->flags.fw_init_done = 0;
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ha->flags.fw_init_done = 0;
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ha->base_qpair->chip_reset++;
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ha->chip_reset++;
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ha->base_qpair->chip_reset = ha->chip_reset;
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for (i = 0; i < ha->max_qpairs; i++) {
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for (i = 0; i < ha->max_qpairs; i++) {
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if (ha->queue_pair_map[i])
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if (ha->queue_pair_map[i])
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ha->queue_pair_map[i]->chip_reset =
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ha->queue_pair_map[i]->chip_reset =
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ha->base_qpair->chip_reset;
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ha->base_qpair->chip_reset;
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}
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}
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/* purge MBox commands */
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if (atomic_read(&ha->num_pend_mbx_stage3)) {
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clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
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complete(&ha->mbx_intr_comp);
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}
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i = 0;
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while (atomic_read(&ha->num_pend_mbx_stage3) ||
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atomic_read(&ha->num_pend_mbx_stage2) ||
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atomic_read(&ha->num_pend_mbx_stage1)) {
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msleep(20);
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i++;
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if (i > 50)
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break;
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}
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ha->flags.purge_mbox = 0;
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atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
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atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
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if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
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if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
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atomic_set(&vha->loop_state, LOOP_DOWN);
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atomic_set(&vha->loop_state, LOOP_DOWN);
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@ -110,6 +110,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
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unsigned long wait_time;
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unsigned long wait_time;
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struct qla_hw_data *ha = vha->hw;
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struct qla_hw_data *ha = vha->hw;
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scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
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scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
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u32 chip_reset;
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ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
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ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
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@ -140,7 +141,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
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rval = QLA_SUCCESS;
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rval = QLA_SUCCESS;
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abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
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abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
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chip_reset = ha->chip_reset;
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if (ha->flags.pci_channel_io_perm_failure) {
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if (ha->flags.pci_channel_io_perm_failure) {
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ql_log(ql_log_warn, vha, 0x1003,
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ql_log(ql_log_warn, vha, 0x1003,
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@ -167,6 +168,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
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return QLA_FUNCTION_TIMEOUT;
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return QLA_FUNCTION_TIMEOUT;
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}
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}
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atomic_inc(&ha->num_pend_mbx_stage1);
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/*
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/*
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* Wait for active mailbox commands to finish by waiting at most tov
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* Wait for active mailbox commands to finish by waiting at most tov
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* seconds. This is to serialize actual issuing of mailbox cmds during
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* seconds. This is to serialize actual issuing of mailbox cmds during
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@ -177,8 +179,14 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
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ql_log(ql_log_warn, vha, 0xd035,
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ql_log(ql_log_warn, vha, 0xd035,
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"Cmd access timeout, cmd=0x%x, Exiting.\n",
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"Cmd access timeout, cmd=0x%x, Exiting.\n",
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mcp->mb[0]);
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mcp->mb[0]);
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atomic_dec(&ha->num_pend_mbx_stage1);
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return QLA_FUNCTION_TIMEOUT;
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return QLA_FUNCTION_TIMEOUT;
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}
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}
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atomic_dec(&ha->num_pend_mbx_stage1);
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if (ha->flags.purge_mbox || chip_reset != ha->chip_reset) {
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rval = QLA_ABORTED;
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goto premature_exit;
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}
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ha->flags.mbox_busy = 1;
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ha->flags.mbox_busy = 1;
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/* Save mailbox command for debug */
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/* Save mailbox command for debug */
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@ -189,6 +197,13 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
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spin_lock_irqsave(&ha->hardware_lock, flags);
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spin_lock_irqsave(&ha->hardware_lock, flags);
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if (ha->flags.purge_mbox || chip_reset != ha->chip_reset) {
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rval = QLA_ABORTED;
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ha->flags.mbox_busy = 0;
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spin_unlock_irqrestore(&ha->hardware_lock, flags);
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goto premature_exit;
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}
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/* Load mailbox registers. */
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/* Load mailbox registers. */
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if (IS_P3P_TYPE(ha))
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if (IS_P3P_TYPE(ha))
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optr = (uint16_t __iomem *)®->isp82.mailbox_in[0];
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optr = (uint16_t __iomem *)®->isp82.mailbox_in[0];
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@ -231,7 +246,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
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"jiffies=%lx.\n", jiffies);
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"jiffies=%lx.\n", jiffies);
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/* Wait for mbx cmd completion until timeout */
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/* Wait for mbx cmd completion until timeout */
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atomic_inc(&ha->num_pend_mbx_stage2);
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if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
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if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
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set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
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set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
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@ -241,6 +256,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
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spin_unlock_irqrestore(&ha->hardware_lock,
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spin_unlock_irqrestore(&ha->hardware_lock,
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flags);
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flags);
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ha->flags.mbox_busy = 0;
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ha->flags.mbox_busy = 0;
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atomic_dec(&ha->num_pend_mbx_stage2);
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ql_dbg(ql_dbg_mbx, vha, 0x1010,
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ql_dbg(ql_dbg_mbx, vha, 0x1010,
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"Pending mailbox timeout, exiting.\n");
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"Pending mailbox timeout, exiting.\n");
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rval = QLA_FUNCTION_TIMEOUT;
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rval = QLA_FUNCTION_TIMEOUT;
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@ -254,6 +270,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
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spin_unlock_irqrestore(&ha->hardware_lock, flags);
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spin_unlock_irqrestore(&ha->hardware_lock, flags);
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wait_time = jiffies;
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wait_time = jiffies;
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atomic_inc(&ha->num_pend_mbx_stage3);
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if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
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if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
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mcp->tov * HZ)) {
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mcp->tov * HZ)) {
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ql_dbg(ql_dbg_mbx, vha, 0x117a,
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ql_dbg(ql_dbg_mbx, vha, 0x117a,
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@ -261,7 +278,17 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
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spin_lock_irqsave(&ha->hardware_lock, flags);
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spin_lock_irqsave(&ha->hardware_lock, flags);
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clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
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clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
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spin_unlock_irqrestore(&ha->hardware_lock, flags);
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spin_unlock_irqrestore(&ha->hardware_lock, flags);
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} else if (ha->flags.purge_mbox ||
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chip_reset != ha->chip_reset) {
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ha->flags.mbox_busy = 0;
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atomic_dec(&ha->num_pend_mbx_stage2);
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atomic_dec(&ha->num_pend_mbx_stage3);
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rval = QLA_ABORTED;
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goto premature_exit;
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}
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}
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atomic_dec(&ha->num_pend_mbx_stage3);
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if (time_after(jiffies, wait_time + 5 * HZ))
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if (time_after(jiffies, wait_time + 5 * HZ))
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ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n",
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ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n",
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command, jiffies_to_msecs(jiffies - wait_time));
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command, jiffies_to_msecs(jiffies - wait_time));
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@ -275,6 +302,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
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spin_unlock_irqrestore(&ha->hardware_lock,
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spin_unlock_irqrestore(&ha->hardware_lock,
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flags);
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flags);
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ha->flags.mbox_busy = 0;
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ha->flags.mbox_busy = 0;
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atomic_dec(&ha->num_pend_mbx_stage2);
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ql_dbg(ql_dbg_mbx, vha, 0x1012,
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ql_dbg(ql_dbg_mbx, vha, 0x1012,
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"Pending mailbox timeout, exiting.\n");
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"Pending mailbox timeout, exiting.\n");
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rval = QLA_FUNCTION_TIMEOUT;
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rval = QLA_FUNCTION_TIMEOUT;
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@ -289,6 +317,14 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
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wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
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wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
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while (!ha->flags.mbox_int) {
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while (!ha->flags.mbox_int) {
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if (ha->flags.purge_mbox ||
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chip_reset != ha->chip_reset) {
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ha->flags.mbox_busy = 0;
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atomic_dec(&ha->num_pend_mbx_stage2);
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rval = QLA_ABORTED;
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goto premature_exit;
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}
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if (time_after(jiffies, wait_time))
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if (time_after(jiffies, wait_time))
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break;
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break;
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@ -312,6 +348,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
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"Waited %d sec.\n",
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"Waited %d sec.\n",
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(uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
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(uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
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}
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}
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atomic_dec(&ha->num_pend_mbx_stage2);
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/* Check whether we timed out */
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/* Check whether we timed out */
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if (ha->flags.mbox_int) {
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if (ha->flags.mbox_int) {
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@ -390,7 +427,8 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
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/* Capture FW dump only, if PCI device active */
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/* Capture FW dump only, if PCI device active */
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if (!pci_channel_offline(vha->hw->pdev)) {
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if (!pci_channel_offline(vha->hw->pdev)) {
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pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
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pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
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if (w == 0xffff || ictrl == 0xffffffff) {
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if (w == 0xffff || ictrl == 0xffffffff ||
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(chip_reset != ha->chip_reset)) {
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/* This is special case if there is unload
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/* This is special case if there is unload
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* of driver happening and if PCI device go
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* of driver happening and if PCI device go
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* into bad state due to PCI error condition
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* into bad state due to PCI error condition
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@ -497,7 +535,11 @@ premature_exit:
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complete(&ha->mbx_cmd_comp);
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complete(&ha->mbx_cmd_comp);
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mbx_done:
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mbx_done:
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if (rval) {
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if (rval == QLA_ABORTED) {
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ql_log(ql_log_info, vha, 0xd035,
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"Chip Reset in progress. Purging Mbox cmd=0x%x.\n",
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mcp->mb[0]);
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} else if (rval) {
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if (ql2xextended_error_logging & (ql_dbg_disc|ql_dbg_mbx)) {
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if (ql2xextended_error_logging & (ql_dbg_disc|ql_dbg_mbx)) {
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pr_warn("%s [%s]-%04x:%ld: **** Failed", QL_MSGHDR,
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pr_warn("%s [%s]-%04x:%ld: **** Failed", QL_MSGHDR,
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dev_name(&ha->pdev->dev), 0x1020+0x800,
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dev_name(&ha->pdev->dev), 0x1020+0x800,
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@ -2815,6 +2815,9 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
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ha->link_data_rate = PORT_SPEED_UNKNOWN;
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ha->link_data_rate = PORT_SPEED_UNKNOWN;
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ha->optrom_size = OPTROM_SIZE_2300;
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ha->optrom_size = OPTROM_SIZE_2300;
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ha->max_exchg = FW_MAX_EXCHANGES_CNT;
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ha->max_exchg = FW_MAX_EXCHANGES_CNT;
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atomic_set(&ha->num_pend_mbx_stage1, 0);
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atomic_set(&ha->num_pend_mbx_stage2, 0);
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atomic_set(&ha->num_pend_mbx_stage3, 0);
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/* Assign ISP specific operations. */
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/* Assign ISP specific operations. */
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if (IS_QLA2100(ha)) {
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if (IS_QLA2100(ha)) {
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