drm/i915/i2c: The bit-banging interface controls the delay, drop ours
Remove our redundant udelay() as the timings are already handled by the i2c-algo-bit controller. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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fe255d0028
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@ -38,16 +38,18 @@
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void intel_i2c_quirk_set(struct drm_device *dev, bool enable)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 val;
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/* When using bit bashing for I2C, this bit needs to be set to 1 */
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if (!IS_PINEVIEW(dev))
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return;
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val = I915_READ(DSPCLK_GATE_D);
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if (enable)
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I915_WRITE(DSPCLK_GATE_D,
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I915_READ(DSPCLK_GATE_D) | DPCUNIT_CLOCK_GATE_DISABLE);
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val |= DPCUNIT_CLOCK_GATE_DISABLE;
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else
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I915_WRITE(DSPCLK_GATE_D,
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I915_READ(DSPCLK_GATE_D) & (~DPCUNIT_CLOCK_GATE_DISABLE));
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val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
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I915_WRITE(DSPCLK_GATE_D, val);
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}
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/*
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@ -60,20 +62,14 @@ static int get_clock(void *data)
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{
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struct intel_i2c_chan *chan = data;
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struct drm_i915_private *dev_priv = chan->drm_dev->dev_private;
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u32 val;
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val = I915_READ(chan->reg);
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return ((val & GPIO_CLOCK_VAL_IN) != 0);
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return (I915_READ(chan->reg) & GPIO_CLOCK_VAL_IN) != 0;
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}
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static int get_data(void *data)
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{
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struct intel_i2c_chan *chan = data;
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struct drm_i915_private *dev_priv = chan->drm_dev->dev_private;
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u32 val;
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val = I915_READ(chan->reg);
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return ((val & GPIO_DATA_VAL_IN) != 0);
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return (I915_READ(chan->reg) & GPIO_DATA_VAL_IN) != 0;
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}
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static void set_clock(void *data, int state_high)
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@ -94,7 +90,7 @@ static void set_clock(void *data, int state_high)
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clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
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GPIO_CLOCK_VAL_MASK;
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I915_WRITE(chan->reg, reserved | clock_bits);
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udelay(I2C_RISEFALL_TIME); /* wait for the line to change state */
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POSTING_READ(chan->reg);
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}
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static void set_data(void *data, int state_high)
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@ -116,7 +112,7 @@ static void set_data(void *data, int state_high)
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GPIO_DATA_VAL_MASK;
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I915_WRITE(chan->reg, reserved | data_bits);
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udelay(I2C_RISEFALL_TIME); /* wait for the line to change state */
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POSTING_READ(chan->reg);
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}
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/* Clears the GMBUS setup. Our driver doesn't make use of the GMBUS I2C
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@ -129,11 +125,10 @@ intel_i2c_reset_gmbus(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (HAS_PCH_SPLIT(dev)) {
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if (HAS_PCH_SPLIT(dev))
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I915_WRITE(PCH_GMBUS0, 0);
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} else {
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else
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I915_WRITE(GMBUS0, 0);
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}
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}
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/**
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@ -177,7 +172,7 @@ struct i2c_adapter *intel_i2c_create(struct drm_device *dev, const u32 reg,
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chan->algo.setscl = set_clock;
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chan->algo.getsda = get_data;
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chan->algo.getscl = get_clock;
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chan->algo.udelay = 20;
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chan->algo.udelay = I2C_RISEFALL_TIME;
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chan->algo.timeout = usecs_to_jiffies(2200);
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chan->algo.data = chan;
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@ -191,9 +186,10 @@ struct i2c_adapter *intel_i2c_create(struct drm_device *dev, const u32 reg,
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/* JJJ: raise SCL and SDA? */
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intel_i2c_quirk_set(dev, true);
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set_data(chan, 1);
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udelay(I2C_RISEFALL_TIME);
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set_clock(chan, 1);
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udelay(I2C_RISEFALL_TIME);
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intel_i2c_quirk_set(dev, false);
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udelay(20);
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return &chan->adapter;
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