clk: meson: gxbb-ao: replace cec-32k with the dual divider
Replace the cec-32k clock of gxbb-ao with the simpler dual divider driver. The dual divider implements only the dividing part. All the other bits are now exposed using simple elements, such as gates and muxes Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20181221160239.26265-5-jbrunet@baylibre.comhifive-unleashed-5.1
Jerome Brunet
Neil Armstrong
parent
a8d552a638
commit
b249623fd1
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@ -7,7 +7,7 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-input.o clk-dualdiv.o
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obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o
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obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
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obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
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obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
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obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
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obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
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obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
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obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
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@ -1,193 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2017 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/bitfield.h>
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#include <linux/regmap.h>
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#include "gxbb-aoclk.h"
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/*
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* The AO Domain embeds a dual/divider to generate a more precise
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* 32,768KHz clock for low-power suspend mode and CEC.
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* ______ ______
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* | | | |
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* ______ | Div1 |-| Cnt1 | ______
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* | | /|______| |______|\ | |
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* Xtal-->| Gate |---| ______ ______ X-X--| Gate |-->
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* |______| | \| | | |/ | |______|
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* | | Div2 |-| Cnt2 | |
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* | |______| |______| |
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* |_______________________|
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*
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* The dividing can be switched to single or dual, with a counter
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* for each divider to set when the switching is done.
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* The entire dividing mechanism can be also bypassed.
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*/
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#define CLK_CNTL0_N1_MASK GENMASK(11, 0)
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#define CLK_CNTL0_N2_MASK GENMASK(23, 12)
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#define CLK_CNTL0_DUALDIV_EN BIT(28)
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#define CLK_CNTL0_OUT_GATE_EN BIT(30)
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#define CLK_CNTL0_IN_GATE_EN BIT(31)
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#define CLK_CNTL1_M1_MASK GENMASK(11, 0)
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#define CLK_CNTL1_M2_MASK GENMASK(23, 12)
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#define CLK_CNTL1_BYPASS_EN BIT(24)
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#define CLK_CNTL1_SELECT_OSC BIT(27)
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#define PWR_CNTL_ALT_32K_SEL GENMASK(13, 10)
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struct cec_32k_freq_table {
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unsigned long parent_rate;
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unsigned long target_rate;
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bool dualdiv;
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unsigned int n1;
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unsigned int n2;
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unsigned int m1;
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unsigned int m2;
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};
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static const struct cec_32k_freq_table aoclk_cec_32k_table[] = {
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[0] = {
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.parent_rate = 24000000,
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.target_rate = 32768,
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.dualdiv = true,
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.n1 = 733,
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.n2 = 732,
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.m1 = 8,
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.m2 = 11,
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},
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};
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/*
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* If CLK_CNTL0_DUALDIV_EN == 0
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* - will use N1 divider only
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* If CLK_CNTL0_DUALDIV_EN == 1
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* - hold M1 cycles of N1 divider then changes to N2
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* - hold M2 cycles of N2 divider then changes to N1
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* Then we can get more accurate division.
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*/
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static unsigned long aoclk_cec_32k_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct aoclk_cec_32k *cec_32k = to_aoclk_cec_32k(hw);
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unsigned long n1;
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u32 reg0, reg1;
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regmap_read(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0, ®0);
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regmap_read(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL1, ®1);
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if (reg1 & CLK_CNTL1_BYPASS_EN)
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return parent_rate;
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if (reg0 & CLK_CNTL0_DUALDIV_EN) {
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unsigned long n2, m1, m2, f1, f2, p1, p2;
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n1 = FIELD_GET(CLK_CNTL0_N1_MASK, reg0) + 1;
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n2 = FIELD_GET(CLK_CNTL0_N2_MASK, reg0) + 1;
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m1 = FIELD_GET(CLK_CNTL1_M1_MASK, reg1) + 1;
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m2 = FIELD_GET(CLK_CNTL1_M2_MASK, reg1) + 1;
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f1 = DIV_ROUND_CLOSEST(parent_rate, n1);
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f2 = DIV_ROUND_CLOSEST(parent_rate, n2);
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p1 = DIV_ROUND_CLOSEST(100000000 * m1, f1 * (m1 + m2));
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p2 = DIV_ROUND_CLOSEST(100000000 * m2, f2 * (m1 + m2));
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return DIV_ROUND_UP(100000000, p1 + p2);
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}
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n1 = FIELD_GET(CLK_CNTL0_N1_MASK, reg0) + 1;
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return DIV_ROUND_CLOSEST(parent_rate, n1);
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}
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static const struct cec_32k_freq_table *find_cec_32k_freq(unsigned long rate,
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unsigned long prate)
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{
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int i;
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for (i = 0 ; i < ARRAY_SIZE(aoclk_cec_32k_table) ; ++i)
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if (aoclk_cec_32k_table[i].parent_rate == prate &&
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aoclk_cec_32k_table[i].target_rate == rate)
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return &aoclk_cec_32k_table[i];
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return NULL;
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}
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static long aoclk_cec_32k_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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const struct cec_32k_freq_table *freq = find_cec_32k_freq(rate,
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*prate);
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/* If invalid return first one */
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if (!freq)
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return aoclk_cec_32k_table[0].target_rate;
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return freq->target_rate;
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}
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/*
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* From the Amlogic init procedure, the IN and OUT gates needs to be handled
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* in the init procedure to avoid any glitches.
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*/
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static int aoclk_cec_32k_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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const struct cec_32k_freq_table *freq = find_cec_32k_freq(rate,
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parent_rate);
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struct aoclk_cec_32k *cec_32k = to_aoclk_cec_32k(hw);
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u32 reg = 0;
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if (!freq)
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return -EINVAL;
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/* Disable clock */
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regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
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CLK_CNTL0_IN_GATE_EN | CLK_CNTL0_OUT_GATE_EN, 0);
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reg = FIELD_PREP(CLK_CNTL0_N1_MASK, freq->n1 - 1);
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if (freq->dualdiv)
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reg |= CLK_CNTL0_DUALDIV_EN |
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FIELD_PREP(CLK_CNTL0_N2_MASK, freq->n2 - 1);
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regmap_write(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0, reg);
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reg = FIELD_PREP(CLK_CNTL1_M1_MASK, freq->m1 - 1);
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if (freq->dualdiv)
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reg |= FIELD_PREP(CLK_CNTL1_M2_MASK, freq->m2 - 1);
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regmap_write(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL1, reg);
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/* Enable clock */
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regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
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CLK_CNTL0_IN_GATE_EN, CLK_CNTL0_IN_GATE_EN);
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udelay(200);
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regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
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CLK_CNTL0_OUT_GATE_EN, CLK_CNTL0_OUT_GATE_EN);
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regmap_update_bits(cec_32k->regmap, AO_CRT_CLK_CNTL1,
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CLK_CNTL1_SELECT_OSC, CLK_CNTL1_SELECT_OSC);
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/* Select 32k from XTAL */
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regmap_update_bits(cec_32k->regmap,
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AO_RTI_PWR_CNTL_REG0,
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PWR_CNTL_ALT_32K_SEL,
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FIELD_PREP(PWR_CNTL_ALT_32K_SEL, 4));
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return 0;
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}
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const struct clk_ops meson_aoclk_cec_32k_ops = {
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.recalc_rate = aoclk_cec_32k_recalc_rate,
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.round_rate = aoclk_cec_32k_round_rate,
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.set_rate = aoclk_cec_32k_set_rate,
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};
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@ -5,10 +5,19 @@
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*/
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#include <linux/platform_device.h>
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#include <linux/mfd/syscon.h>
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#include "clk-regmap.h"
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#include "clkc.h"
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#include "meson-aoclk.h"
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#include "gxbb-aoclk.h"
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/* AO Configuration Clock registers offsets */
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#define AO_RTI_PWR_CNTL_REG1 0x0c
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#define AO_RTI_PWR_CNTL_REG0 0x10
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#define AO_RTI_GEN_CNTL_REG0 0x40
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#define AO_OSCIN_CNTL 0x58
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#define AO_CRT_CLK_CNTL1 0x68
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#define AO_RTC_ALT_CLK_CNTL0 0x94
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#define AO_RTC_ALT_CLK_CNTL1 0x98
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#define GXBB_AO_GATE(_name, _bit) \
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static struct clk_regmap _name##_ao = { \
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.data = &(struct clk_regmap_gate_data) { \
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@ -31,13 +40,174 @@ GXBB_AO_GATE(uart1, 3);
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GXBB_AO_GATE(uart2, 5);
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GXBB_AO_GATE(ir_blaster, 6);
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static struct aoclk_cec_32k cec_32k_ao = {
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.hw.init = &(struct clk_init_data) {
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.name = "cec_32k_ao",
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.ops = &meson_aoclk_cec_32k_ops,
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static struct clk_regmap ao_cts_oscin = {
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.data = &(struct clk_regmap_gate_data){
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.offset = AO_RTI_PWR_CNTL_REG0,
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.bit_idx = 6,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ao_cts_oscin",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_names = (const char *[]){ "xtal" },
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.num_parents = 1,
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.flags = CLK_IGNORE_UNUSED,
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},
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};
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static struct clk_regmap ao_32k_pre = {
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.data = &(struct clk_regmap_gate_data){
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.offset = AO_RTC_ALT_CLK_CNTL0,
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.bit_idx = 31,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ao_32k_pre",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "ao_cts_oscin" },
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.num_parents = 1,
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},
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};
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static const struct meson_clk_dualdiv_param gxbb_32k_div_table[] = {
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{
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.dual = 1,
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.n1 = 733,
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.m1 = 8,
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.n2 = 732,
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.m2 = 11,
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}, {}
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};
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static struct clk_regmap ao_32k_div = {
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.data = &(struct meson_clk_dualdiv_data){
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.n1 = {
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.reg_off = AO_RTC_ALT_CLK_CNTL0,
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.shift = 0,
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.width = 12,
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},
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.n2 = {
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.reg_off = AO_RTC_ALT_CLK_CNTL0,
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.shift = 12,
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.width = 12,
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},
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.m1 = {
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.reg_off = AO_RTC_ALT_CLK_CNTL1,
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.shift = 0,
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.width = 12,
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},
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.m2 = {
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.reg_off = AO_RTC_ALT_CLK_CNTL1,
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.shift = 12,
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.width = 12,
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},
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.dual = {
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.reg_off = AO_RTC_ALT_CLK_CNTL0,
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.shift = 28,
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.width = 1,
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},
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.table = gxbb_32k_div_table,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ao_32k_div",
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.ops = &meson_clk_dualdiv_ops,
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.parent_names = (const char *[]){ "ao_32k_pre" },
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.num_parents = 1,
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},
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};
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static struct clk_regmap ao_32k_sel = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_RTC_ALT_CLK_CNTL1,
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.mask = 0x1,
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.shift = 24,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ao_32k_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = (const char *[]){ "ao_32k_div",
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"ao_32k_pre" },
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap ao_32k = {
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.data = &(struct clk_regmap_gate_data){
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.offset = AO_RTC_ALT_CLK_CNTL0,
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.bit_idx = 30,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ao_32k",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "ao_32k_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap ao_cts_rtc_oscin = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_RTI_PWR_CNTL_REG0,
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.mask = 0x7,
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.shift = 10,
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.table = (u32[]){ 1, 2, 3, 4 },
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ao_cts_rtc_oscin",
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.ops = &clk_regmap_mux_ops,
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.parent_names = (const char *[]){ "ext_32k_0",
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"ext_32k_1",
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"ext_32k_2",
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"ao_32k" },
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.num_parents = 4,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap ao_clk81 = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_RTI_PWR_CNTL_REG0,
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.mask = 0x1,
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.shift = 0,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ao_clk81",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_names = (const char *[]){ "clk81",
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"ao_cts_rtc_oscin" },
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap ao_cts_cec = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_CRT_CLK_CNTL1,
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.mask = 0x1,
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.shift = 27,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ao_cts_cec",
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.ops = &clk_regmap_mux_ops,
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/*
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* FIXME: The 'fixme' parent obviously does not exist.
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*
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* ATM, CCF won't call get_parent() if num_parents is 1. It
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* does not allow NULL as a parent name either.
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*
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* On this particular mux, we only know the input #1 parent
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* but, on boot, unknown input #0 is set, so it is critical
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* to call .get_parent() on it
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*
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* Until CCF gets fixed, adding this fake parent that won't
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* ever be registered should work around the problem
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*/
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.parent_names = (const char *[]){ "fixme",
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"ao_cts_rtc_oscin" },
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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@ -50,13 +220,21 @@ static const unsigned int gxbb_aoclk_reset[] = {
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[RESET_AO_IR_BLASTER] = 23,
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};
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static struct clk_regmap *gxbb_aoclk_gate[] = {
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[CLKID_AO_REMOTE] = &remote_ao,
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[CLKID_AO_I2C_MASTER] = &i2c_master_ao,
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[CLKID_AO_I2C_SLAVE] = &i2c_slave_ao,
|
||||
[CLKID_AO_UART1] = &uart1_ao,
|
||||
[CLKID_AO_UART2] = &uart2_ao,
|
||||
[CLKID_AO_IR_BLASTER] = &ir_blaster_ao,
|
||||
static struct clk_regmap *gxbb_aoclk[] = {
|
||||
&remote_ao,
|
||||
&i2c_master_ao,
|
||||
&i2c_slave_ao,
|
||||
&uart1_ao,
|
||||
&uart2_ao,
|
||||
&ir_blaster_ao,
|
||||
&ao_cts_oscin,
|
||||
&ao_32k_pre,
|
||||
&ao_32k_div,
|
||||
&ao_32k_sel,
|
||||
&ao_32k,
|
||||
&ao_cts_rtc_oscin,
|
||||
&ao_clk81,
|
||||
&ao_cts_cec,
|
||||
};
|
||||
|
||||
static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
|
||||
|
|
@ -67,52 +245,27 @@ static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
|
|||
[CLKID_AO_UART1] = &uart1_ao.hw,
|
||||
[CLKID_AO_UART2] = &uart2_ao.hw,
|
||||
[CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
|
||||
[CLKID_AO_CEC_32K] = &cec_32k_ao.hw,
|
||||
[CLKID_AO_CEC_32K] = &ao_cts_cec.hw,
|
||||
[CLKID_AO_CTS_OSCIN] = &ao_cts_oscin.hw,
|
||||
[CLKID_AO_32K_PRE] = &ao_32k_pre.hw,
|
||||
[CLKID_AO_32K_DIV] = &ao_32k_div.hw,
|
||||
[CLKID_AO_32K_SEL] = &ao_32k_sel.hw,
|
||||
[CLKID_AO_32K] = &ao_32k.hw,
|
||||
[CLKID_AO_CTS_RTC_OSCIN] = &ao_cts_rtc_oscin.hw,
|
||||
[CLKID_AO_CLK81] = &ao_clk81.hw,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
};
|
||||
|
||||
static int gxbb_register_cec_ao_32k(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
|
||||
if (IS_ERR(regmap)) {
|
||||
dev_err(dev, "failed to get regmap\n");
|
||||
return PTR_ERR(regmap);
|
||||
}
|
||||
|
||||
/* Specific clocks */
|
||||
cec_32k_ao.regmap = regmap;
|
||||
ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "clk cec_32k_ao register failed.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct meson_aoclk_data gxbb_aoclkc_data = {
|
||||
.reset_reg = AO_RTI_GEN_CNTL_REG0,
|
||||
.num_reset = ARRAY_SIZE(gxbb_aoclk_reset),
|
||||
.reset = gxbb_aoclk_reset,
|
||||
.num_clks = ARRAY_SIZE(gxbb_aoclk_gate),
|
||||
.clks = gxbb_aoclk_gate,
|
||||
.num_clks = ARRAY_SIZE(gxbb_aoclk),
|
||||
.clks = gxbb_aoclk,
|
||||
.hw_data = &gxbb_aoclk_onecell_data,
|
||||
};
|
||||
|
||||
static int gxbb_aoclkc_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret = gxbb_register_cec_ao_32k(pdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return meson_aoclkc_probe(pdev);
|
||||
}
|
||||
|
||||
static const struct of_device_id gxbb_aoclkc_match_table[] = {
|
||||
{
|
||||
.compatible = "amlogic,meson-gx-aoclkc",
|
||||
|
|
@ -122,7 +275,7 @@ static const struct of_device_id gxbb_aoclkc_match_table[] = {
|
|||
};
|
||||
|
||||
static struct platform_driver gxbb_aoclkc_driver = {
|
||||
.probe = gxbb_aoclkc_probe,
|
||||
.probe = meson_aoclkc_probe,
|
||||
.driver = {
|
||||
.name = "gxbb-aoclkc",
|
||||
.of_match_table = gxbb_aoclkc_match_table,
|
||||
|
|
|
|||
|
|
@ -7,25 +7,7 @@
|
|||
#ifndef __GXBB_AOCLKC_H
|
||||
#define __GXBB_AOCLKC_H
|
||||
|
||||
#define NR_CLKS 7
|
||||
|
||||
/* AO Configuration Clock registers offsets */
|
||||
#define AO_RTI_PWR_CNTL_REG1 0x0c
|
||||
#define AO_RTI_PWR_CNTL_REG0 0x10
|
||||
#define AO_RTI_GEN_CNTL_REG0 0x40
|
||||
#define AO_OSCIN_CNTL 0x58
|
||||
#define AO_CRT_CLK_CNTL1 0x68
|
||||
#define AO_RTC_ALT_CLK_CNTL0 0x94
|
||||
#define AO_RTC_ALT_CLK_CNTL1 0x98
|
||||
|
||||
struct aoclk_cec_32k {
|
||||
struct clk_hw hw;
|
||||
struct regmap *regmap;
|
||||
};
|
||||
|
||||
#define to_aoclk_cec_32k(_hw) container_of(_hw, struct aoclk_cec_32k, hw)
|
||||
|
||||
extern const struct clk_ops meson_aoclk_cec_32k_ops;
|
||||
#define NR_CLKS 14
|
||||
|
||||
#include <dt-bindings/clock/gxbb-aoclkc.h>
|
||||
#include <dt-bindings/reset/gxbb-aoclkc.h>
|
||||
|
|
|
|||
Loading…
Reference in New Issue