mfd: bd9571mwv: Add support for BD9574MWF
The new PMIC BD9574MWF inherits features from BD9571MWV. Add the support of new PMIC to existing bd9571mwv driver. Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com> Co-developed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>master
Khiem Nguyen
Lee Jones
parent
f16e1fd197
commit
b2548da647
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* ROHM BD9571MWV-M MFD driver
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* ROHM BD9571MWV-M and BD9574MVF-M core driver
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*
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* Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
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* Copyright (C) 2020 Renesas Electronics Corporation
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@ -11,6 +11,7 @@
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/rohm-generic.h>
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#include <linux/module.h>
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#include <linux/mfd/bd9571mwv.h>
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@ -103,6 +104,72 @@ static struct regmap_irq_chip bd9571mwv_irq_chip = {
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.num_irqs = ARRAY_SIZE(bd9571mwv_irqs),
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};
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static const struct mfd_cell bd9574mwf_cells[] = {
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{ .name = "bd9574mwf-regulator", },
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{ .name = "bd9574mwf-gpio", },
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};
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static const struct regmap_range bd9574mwf_readable_yes_ranges[] = {
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regmap_reg_range(BD9571MWV_VENDOR_CODE, BD9571MWV_PRODUCT_REVISION),
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regmap_reg_range(BD9571MWV_BKUP_MODE_CNT, BD9571MWV_BKUP_MODE_CNT),
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regmap_reg_range(BD9571MWV_DVFS_VINIT, BD9571MWV_DVFS_SETVMAX),
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regmap_reg_range(BD9571MWV_DVFS_SETVID, BD9571MWV_DVFS_MONIVDAC),
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regmap_reg_range(BD9571MWV_GPIO_IN, BD9571MWV_GPIO_IN),
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regmap_reg_range(BD9571MWV_GPIO_INT, BD9571MWV_GPIO_INTMASK),
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regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTMASK),
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};
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static const struct regmap_access_table bd9574mwf_readable_table = {
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.yes_ranges = bd9574mwf_readable_yes_ranges,
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.n_yes_ranges = ARRAY_SIZE(bd9574mwf_readable_yes_ranges),
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};
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static const struct regmap_range bd9574mwf_writable_yes_ranges[] = {
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regmap_reg_range(BD9571MWV_BKUP_MODE_CNT, BD9571MWV_BKUP_MODE_CNT),
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regmap_reg_range(BD9571MWV_DVFS_SETVID, BD9571MWV_DVFS_SETVID),
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regmap_reg_range(BD9571MWV_GPIO_DIR, BD9571MWV_GPIO_OUT),
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regmap_reg_range(BD9571MWV_GPIO_INT_SET, BD9571MWV_GPIO_INTMASK),
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regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTMASK),
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};
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static const struct regmap_access_table bd9574mwf_writable_table = {
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.yes_ranges = bd9574mwf_writable_yes_ranges,
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.n_yes_ranges = ARRAY_SIZE(bd9574mwf_writable_yes_ranges),
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};
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static const struct regmap_range bd9574mwf_volatile_yes_ranges[] = {
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regmap_reg_range(BD9571MWV_DVFS_MONIVDAC, BD9571MWV_DVFS_MONIVDAC),
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regmap_reg_range(BD9571MWV_GPIO_IN, BD9571MWV_GPIO_IN),
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regmap_reg_range(BD9571MWV_GPIO_INT, BD9571MWV_GPIO_INT),
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regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTREQ),
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};
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static const struct regmap_access_table bd9574mwf_volatile_table = {
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.yes_ranges = bd9574mwf_volatile_yes_ranges,
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.n_yes_ranges = ARRAY_SIZE(bd9574mwf_volatile_yes_ranges),
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};
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static const struct regmap_config bd9574mwf_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.cache_type = REGCACHE_RBTREE,
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.rd_table = &bd9574mwf_readable_table,
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.wr_table = &bd9574mwf_writable_table,
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.volatile_table = &bd9574mwf_volatile_table,
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.max_register = 0xff,
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};
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static struct regmap_irq_chip bd9574mwf_irq_chip = {
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.name = "bd9574mwf",
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.status_base = BD9571MWV_INT_INTREQ,
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.mask_base = BD9571MWV_INT_INTMASK,
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.ack_base = BD9571MWV_INT_INTREQ,
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.init_ack_masked = true,
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.num_regs = 1,
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.irqs = bd9571mwv_irqs,
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.num_irqs = ARRAY_SIZE(bd9571mwv_irqs),
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};
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static int bd957x_identify(struct device *dev, struct regmap *regmap)
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{
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unsigned int value;
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@ -162,6 +229,12 @@ static int bd9571mwv_probe(struct i2c_client *client,
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cells = bd9571mwv_cells;
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num_cells = ARRAY_SIZE(bd9571mwv_cells);
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break;
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case BD9571MWV_PRODUCT_CODE_BD9574MWF:
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regmap_config = &bd9574mwf_regmap_config;
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irq_chip = &bd9574mwf_irq_chip;
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cells = bd9574mwf_cells;
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num_cells = ARRAY_SIZE(bd9574mwf_cells);
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break;
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default:
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dev_err(dev, "Unsupported device 0x%x\n", ret);
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return -ENODEV;
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@ -190,6 +263,7 @@ static int bd9571mwv_probe(struct i2c_client *client,
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static const struct of_device_id bd9571mwv_of_match_table[] = {
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{ .compatible = "rohm,bd9571mwv", },
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{ .compatible = "rohm,bd9574mwf", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, bd9571mwv_of_match_table);
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* ROHM BD9571MWV-M driver
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* ROHM BD9571MWV-M and BD9574MWF-M driver
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*
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* Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
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* Copyright (C) 2020 Renesas Electronics Corporation
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@ -14,11 +14,12 @@
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#include <linux/device.h>
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#include <linux/regmap.h>
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/* List of registers for BD9571MWV */
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/* List of registers for BD9571MWV and BD9574MWF */
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#define BD9571MWV_VENDOR_CODE 0x00
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#define BD9571MWV_VENDOR_CODE_VAL 0xdb
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#define BD9571MWV_PRODUCT_CODE 0x01
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#define BD9571MWV_PRODUCT_CODE_BD9571MWV 0x60
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#define BD9571MWV_PRODUCT_CODE_BD9574MWF 0x74
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#define BD9571MWV_PRODUCT_REVISION 0x02
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#define BD9571MWV_I2C_FUSA_MODE 0x10
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@ -48,6 +49,7 @@
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#define BD9571MWV_VD33_VID 0x44
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#define BD9571MWV_DVFS_VINIT 0x50
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#define BD9574MWF_VD09_VINIT 0x51
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#define BD9571MWV_DVFS_SETVMAX 0x52
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#define BD9571MWV_DVFS_BOOSTVID 0x53
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#define BD9571MWV_DVFS_SETVID 0x54
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@ -61,6 +63,7 @@
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#define BD9571MWV_GPIO_INT_SET 0x64
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#define BD9571MWV_GPIO_INT 0x65
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#define BD9571MWV_GPIO_INTMASK 0x66
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#define BD9574MWF_GPIO_MUX 0x67
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#define BD9571MWV_REG_KEEP(n) (0x70 + (n))
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@ -70,6 +73,8 @@
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#define BD9571MWV_PROT_ERROR_STATUS2 0x83
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#define BD9571MWV_PROT_ERROR_STATUS3 0x84
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#define BD9571MWV_PROT_ERROR_STATUS4 0x85
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#define BD9574MWF_PROT_ERROR_STATUS5 0x86
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#define BD9574MWF_SYSTEM_ERROR_STATUS 0x87
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#define BD9571MWV_INT_INTREQ 0x90
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#define BD9571MWV_INT_INTREQ_MD1_INT BIT(0)
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@ -82,6 +87,12 @@
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#define BD9571MWV_INT_INTREQ_BKUP_TRG_INT BIT(7)
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#define BD9571MWV_INT_INTMASK 0x91
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#define BD9574MWF_SSCG_CNT 0xA0
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#define BD9574MWF_POFFB_MRB 0xA1
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#define BD9574MWF_SMRB_WR_PROT 0xA2
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#define BD9574MWF_SMRB_ASSERT 0xA3
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#define BD9574MWF_SMRB_STATUS 0xA4
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#define BD9571MWV_ACCESS_KEY 0xff
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/* Define the BD9571MWV IRQ numbers */
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@ -91,7 +102,7 @@ enum bd9571mwv_irqs {
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BD9571MWV_IRQ_MD2_E2,
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BD9571MWV_IRQ_PROT_ERR,
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BD9571MWV_IRQ_GP,
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BD9571MWV_IRQ_128H_OF,
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BD9571MWV_IRQ_128H_OF, /* BKUP_HOLD on BD9574MWF */
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BD9571MWV_IRQ_WDT_OF,
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BD9571MWV_IRQ_BKUP_TRG,
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};
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