drm/i915/gvt: Add new 64K entry type
Add a new entry type GTT_TYPE_PPGTT_PTE_64K_ENTRY. 64K entry is very different from 2M/1G entry. 64K entry is controlled by IPS bit in upper PDE. To leverage the current logic, I take IPS bit as 'PSE' for PTE level. Which means, 64K entries can also processed by get_pse_type(). v2: Make it bisectable. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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@ -216,16 +216,22 @@ static struct gtt_type_table_entry gtt_type_table[] = {
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GTT_TYPE_PPGTT_PDE_PT,
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GTT_TYPE_PPGTT_PTE_PT,
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GTT_TYPE_PPGTT_PTE_2M_ENTRY),
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/* We take IPS bit as 'PSE' for PTE level. */
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GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT,
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GTT_TYPE_PPGTT_PTE_4K_ENTRY,
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GTT_TYPE_PPGTT_PTE_PT,
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GTT_TYPE_INVALID,
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GTT_TYPE_INVALID),
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GTT_TYPE_PPGTT_PTE_64K_ENTRY),
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GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY,
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GTT_TYPE_PPGTT_PTE_4K_ENTRY,
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GTT_TYPE_PPGTT_PTE_PT,
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GTT_TYPE_INVALID,
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GTT_TYPE_INVALID),
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GTT_TYPE_PPGTT_PTE_64K_ENTRY),
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GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_64K_ENTRY,
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GTT_TYPE_PPGTT_PTE_4K_ENTRY,
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GTT_TYPE_PPGTT_PTE_PT,
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GTT_TYPE_INVALID,
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GTT_TYPE_PPGTT_PTE_64K_ENTRY),
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GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY,
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GTT_TYPE_PPGTT_PDE_ENTRY,
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GTT_TYPE_PPGTT_PDE_PT,
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@ -339,6 +345,7 @@ static inline int gtt_set_entry64(void *pt,
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#define ADDR_1G_MASK GENMASK_ULL(GTT_HAW - 1, 30)
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#define ADDR_2M_MASK GENMASK_ULL(GTT_HAW - 1, 21)
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#define ADDR_64K_MASK GENMASK_ULL(GTT_HAW - 1, 16)
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#define ADDR_4K_MASK GENMASK_ULL(GTT_HAW - 1, 12)
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static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
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@ -349,6 +356,8 @@ static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
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pfn = (e->val64 & ADDR_1G_MASK) >> PAGE_SHIFT;
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else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY)
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pfn = (e->val64 & ADDR_2M_MASK) >> PAGE_SHIFT;
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else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY)
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pfn = (e->val64 & ADDR_64K_MASK) >> PAGE_SHIFT;
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else
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pfn = (e->val64 & ADDR_4K_MASK) >> PAGE_SHIFT;
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return pfn;
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@ -362,6 +371,9 @@ static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry *e, unsigned long pfn)
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} else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) {
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e->val64 &= ~ADDR_2M_MASK;
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pfn &= (ADDR_2M_MASK >> PAGE_SHIFT);
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} else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY) {
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e->val64 &= ~ADDR_64K_MASK;
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pfn &= (ADDR_64K_MASK >> PAGE_SHIFT);
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} else {
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e->val64 &= ~ADDR_4K_MASK;
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pfn &= (ADDR_4K_MASK >> PAGE_SHIFT);
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@ -380,6 +392,10 @@ static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
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if (!(e->val64 & _PAGE_PSE))
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return false;
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/* We don't support 64K entry yet, will remove this later. */
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if (get_pse_type(e->type) == GTT_TYPE_PPGTT_PTE_64K_ENTRY)
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return false;
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e->type = get_pse_type(e->type);
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return true;
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}
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@ -871,9 +887,10 @@ static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
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gvt_vdbg_mm("invalidate 4K entry\n");
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ppgtt_invalidate_pte(spt, &e);
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break;
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case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
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case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
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case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
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WARN(1, "GVT doesn't support 2M/1GB page\n");
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WARN(1, "GVT doesn't support 64K/2M/1GB page\n");
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continue;
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case GTT_TYPE_PPGTT_PML4_ENTRY:
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case GTT_TYPE_PPGTT_PDP_ENTRY:
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@ -970,9 +987,10 @@ static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu,
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case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
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gvt_vdbg_mm("shadow 4K gtt entry\n");
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break;
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case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
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case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
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case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
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gvt_vgpu_err("GVT doesn't support 2M/1GB entry\n");
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gvt_vgpu_err("GVT doesn't support 64K/2M/1GB entry\n");
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return -EINVAL;
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default:
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GEM_BUG_ON(1);
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@ -95,6 +95,7 @@ typedef enum {
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GTT_TYPE_GGTT_PTE,
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GTT_TYPE_PPGTT_PTE_4K_ENTRY,
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GTT_TYPE_PPGTT_PTE_64K_ENTRY,
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GTT_TYPE_PPGTT_PTE_2M_ENTRY,
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GTT_TYPE_PPGTT_PTE_1G_ENTRY,
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