soc: samsung: pm_domains: Deprecate support for clocks
Handling of special clock operations on power domain on/off sequences has been moved to respective Exynos clock controller drivers, so there is no need to keep the duplicated (and conflicting) code in Exynos power domain driver. Mark clock related properties in Exynos power domain bindings as deprecated. This change has no inpact on backwards-compatibility, as the new drivers properly work with old DTBs (deprecated properties are ignored). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>hifive-unleashed-5.1
Marek Szyprowski
Krzysztof Kozlowski
parent
60cc43fc88
commit
b2b568c591
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@ -15,23 +15,13 @@ Required Properties:
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Optional Properties:
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- label: Human readable string with domain name. Will be visible in userspace
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to let user to distinguish between multiple domains in SoC.
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- clocks: List of clock handles. The parent clocks of the input clocks to the
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devices in this power domain are set to oscclk before power gating
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and restored back after powering on a domain. This is required for
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all domains which are powered on and off and not required for unused
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domains.
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- clock-names: The following clocks can be specified:
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- oscclk: Oscillator clock.
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- clkN: Input clocks to the devices in this power domain. These clocks
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will be reparented to oscclk before switching power domain off.
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Their original parent will be brought back after turning on
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the domain. Maximum of 4 clocks (N = 0 to 3) are supported.
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- asbN: Clocks required by asynchronous bridges (ASB) present in
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the power domain. These clock should be enabled during power
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domain on/off operations.
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- power-domains: phandle pointing to the parent power domain, for more details
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see Documentation/devicetree/bindings/power/power_domain.txt
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Deprecated Properties:
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- clocks
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- clock-names
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Node of a device using power domains must have a power-domains property
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defined with a phandle to respective power domain.
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@ -47,8 +37,6 @@ Example:
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mfc_pd: power-domain@10044060 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044060 0x20>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
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clock-names = "oscclk", "clk0";
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#power-domain-cells = <0>;
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label = "MFC";
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};
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@ -13,14 +13,11 @@
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/pm_domain.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/sched.h>
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#define MAX_CLK_PER_DOMAIN 4
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struct exynos_pm_domain_config {
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/* Value for LOCAL_PWR_CFG and STATUS fields for each domain */
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u32 local_pwr_cfg;
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@ -33,10 +30,6 @@ struct exynos_pm_domain {
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void __iomem *base;
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bool is_off;
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struct generic_pm_domain pd;
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struct clk *oscclk;
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struct clk *clk[MAX_CLK_PER_DOMAIN];
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struct clk *pclk[MAX_CLK_PER_DOMAIN];
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struct clk *asb_clk[MAX_CLK_PER_DOMAIN];
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u32 local_pwr_cfg;
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};
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@ -46,29 +39,10 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
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void __iomem *base;
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u32 timeout, pwr;
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char *op;
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int i;
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pd = container_of(domain, struct exynos_pm_domain, pd);
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base = pd->base;
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for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
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if (IS_ERR(pd->asb_clk[i]))
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break;
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clk_prepare_enable(pd->asb_clk[i]);
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}
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/* Set oscclk before powering off a domain*/
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if (!power_on) {
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for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
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if (IS_ERR(pd->clk[i]))
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break;
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pd->pclk[i] = clk_get_parent(pd->clk[i]);
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if (clk_set_parent(pd->clk[i], pd->oscclk))
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pr_err("%s: error setting oscclk as parent to clock %d\n",
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domain->name, i);
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}
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}
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pwr = power_on ? pd->local_pwr_cfg : 0;
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writel_relaxed(pwr, base);
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@ -86,26 +60,6 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
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usleep_range(80, 100);
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}
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/* Restore clocks after powering on a domain*/
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if (power_on) {
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for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
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if (IS_ERR(pd->clk[i]))
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break;
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if (IS_ERR(pd->pclk[i]))
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continue; /* Skip on first power up */
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if (clk_set_parent(pd->clk[i], pd->pclk[i]))
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pr_err("%s: error setting parent to clock%d\n",
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domain->name, i);
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}
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}
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for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
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if (IS_ERR(pd->asb_clk[i]))
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break;
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clk_disable_unprepare(pd->asb_clk[i]);
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}
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return 0;
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}
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@ -147,12 +101,6 @@ static __init const char *exynos_get_domain_name(struct device_node *node)
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return kstrdup_const(name, GFP_KERNEL);
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}
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static const char *soc_force_no_clk[] = {
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"samsung,exynos5250-clock",
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"samsung,exynos5420-clock",
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"samsung,exynos5800-clock",
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};
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static __init int exynos4_pm_init_power_domain(void)
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{
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struct device_node *np;
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@ -161,7 +109,7 @@ static __init int exynos4_pm_init_power_domain(void)
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for_each_matching_node_and_match(np, exynos_pm_domain_of_match, &match) {
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const struct exynos_pm_domain_config *pm_domain_cfg;
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struct exynos_pm_domain *pd;
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int on, i;
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int on;
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pm_domain_cfg = match->data;
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@ -189,42 +137,6 @@ static __init int exynos4_pm_init_power_domain(void)
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pd->pd.power_on = exynos_pd_power_on;
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pd->local_pwr_cfg = pm_domain_cfg->local_pwr_cfg;
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for (i = 0; i < ARRAY_SIZE(soc_force_no_clk); i++)
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if (of_find_compatible_node(NULL, NULL,
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soc_force_no_clk[i]))
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goto no_clk;
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for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
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char clk_name[8];
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snprintf(clk_name, sizeof(clk_name), "asb%d", i);
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pd->asb_clk[i] = of_clk_get_by_name(np, clk_name);
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if (IS_ERR(pd->asb_clk[i]))
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break;
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}
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pd->oscclk = of_clk_get_by_name(np, "oscclk");
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if (IS_ERR(pd->oscclk))
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goto no_clk;
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for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
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char clk_name[8];
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snprintf(clk_name, sizeof(clk_name), "clk%d", i);
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pd->clk[i] = of_clk_get_by_name(np, clk_name);
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if (IS_ERR(pd->clk[i]))
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break;
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/*
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* Skip setting parent on first power up.
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* The parent at this time may not be useful at all.
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*/
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pd->pclk[i] = ERR_PTR(-EINVAL);
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}
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if (IS_ERR(pd->clk[0]))
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clk_put(pd->oscclk);
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no_clk:
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on = readl_relaxed(pd->base + 0x4) & pd->local_pwr_cfg;
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pm_genpd_init(&pd->pd, NULL, !on);
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