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@ -34,6 +34,63 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
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link_status[3], link_status[4], link_status[5]);
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}
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static int intel_dp_lttpr_count(struct intel_dp *intel_dp)
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{
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int count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
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/*
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* Pretend no LTTPRs in case of LTTPR detection error, or
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* if too many (>8) LTTPRs are detected. This translates to link
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* training in transparent mode.
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*/
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return count <= 0 ? 0 : count;
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}
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static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp)
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{
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intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -
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DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0;
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}
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static const char *intel_dp_phy_name(enum drm_dp_phy dp_phy,
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char *buf, size_t buf_size)
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{
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if (dp_phy == DP_PHY_DPRX)
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snprintf(buf, buf_size, "DPRX");
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else
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snprintf(buf, buf_size, "LTTPR %d", dp_phy - DP_PHY_LTTPR1 + 1);
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return buf;
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}
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static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
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enum drm_dp_phy dp_phy)
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{
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return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1];
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}
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static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
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enum drm_dp_phy dp_phy)
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{
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u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
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char phy_name[10];
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intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
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if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) {
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drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
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"failed to read the PHY caps for %s\n",
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phy_name);
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return;
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}
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drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
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"%s PHY capabilities: %*ph\n",
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phy_name,
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(int)sizeof(intel_dp->lttpr_phy_caps[0]),
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phy_caps);
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}
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static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
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{
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if (drm_dp_read_lttpr_common_caps(&intel_dp->aux,
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@ -64,24 +121,64 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
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* intel_dp_lttpr_init - detect LTTPRs and init the LTTPR link training mode
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* @intel_dp: Intel DP struct
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*
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* Read the LTTPR common capabilities and switch to transparent link training
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* mode.
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* Read the LTTPR common capabilities, switch to non-transparent link training
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* mode if any is detected and read the PHY capabilities for all detected
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* LTTPRs. In case of an LTTPR detection error or if the number of
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* LTTPRs is more than is supported (8), fall back to the no-LTTPR,
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* transparent mode link training mode.
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*
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* Returns:
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* >0 if LTTPRs were detected and the non-transparent LT mode was set
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* 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a
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* detection failure and the transparent LT mode was set
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*/
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int intel_dp_lttpr_init(struct intel_dp *intel_dp)
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{
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int lttpr_count;
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bool ret;
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int i;
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if (intel_dp_is_edp(intel_dp))
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return 0;
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intel_dp_read_lttpr_common_caps(intel_dp);
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ret = intel_dp_read_lttpr_common_caps(intel_dp);
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/*
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* See DP Standard v2.0 3.6.6.1. about the explicit disabling of
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* non-transparent mode.
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* non-transparent mode and the disable->enable non-transparent mode
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* sequence.
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*/
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intel_dp_set_lttpr_transparent_mode(intel_dp, true);
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return 0;
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if (!ret)
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return 0;
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lttpr_count = intel_dp_lttpr_count(intel_dp);
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/*
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* In case of unsupported number of LTTPRs or failing to switch to
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* non-transparent mode fall-back to transparent link training mode,
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* still taking into account any LTTPR common lane- rate/count limits.
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*/
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if (lttpr_count == 0)
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return 0;
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if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) {
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drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
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"Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n");
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intel_dp_set_lttpr_transparent_mode(intel_dp, true);
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intel_dp_reset_lttpr_count(intel_dp);
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return 0;
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}
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for (i = 0; i < lttpr_count; i++)
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intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i));
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return lttpr_count;
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}
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EXPORT_SYMBOL(intel_dp_lttpr_init);
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static u8 dp_voltage_max(u8 preemph)
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{
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@ -98,12 +195,91 @@ static u8 dp_voltage_max(u8 preemph)
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}
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}
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static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp,
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enum drm_dp_phy dp_phy)
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{
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const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
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if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps))
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return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
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else
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return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
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}
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static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp,
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enum drm_dp_phy dp_phy)
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{
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const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
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if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps))
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return DP_TRAIN_PRE_EMPH_LEVEL_3;
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else
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return DP_TRAIN_PRE_EMPH_LEVEL_2;
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}
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static bool
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intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp,
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enum drm_dp_phy dp_phy)
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{
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struct drm_i915_private *i915 = dp_to_i915(intel_dp);
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int lttpr_count = intel_dp_lttpr_count(intel_dp);
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drm_WARN_ON_ONCE(&i915->drm, lttpr_count == 0 && dp_phy != DP_PHY_DPRX);
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return lttpr_count == 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1);
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}
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static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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enum drm_dp_phy dp_phy)
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{
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struct drm_i915_private *i915 = dp_to_i915(intel_dp);
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u8 voltage_max;
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/*
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* Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from
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* the DPRX_PHY we train.
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*/
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if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
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voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);
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else
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voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1);
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drm_WARN_ON_ONCE(&i915->drm,
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voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
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voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);
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return voltage_max;
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}
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static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,
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enum drm_dp_phy dp_phy)
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{
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struct drm_i915_private *i915 = dp_to_i915(intel_dp);
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u8 preemph_max;
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/*
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* Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from
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* the DPRX_PHY we train.
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*/
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if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
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preemph_max = intel_dp->preemph_max(intel_dp);
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else
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preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1);
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drm_WARN_ON_ONCE(&i915->drm,
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preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 &&
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preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3);
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return preemph_max;
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}
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void
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intel_dp_get_adjust_train(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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enum drm_dp_phy dp_phy,
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const u8 link_status[DP_LINK_STATUS_SIZE])
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{
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struct drm_i915_private *i915 = dp_to_i915(intel_dp);
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u8 v = 0;
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u8 p = 0;
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int lane;
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@ -115,21 +291,13 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
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p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
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}
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preemph_max = intel_dp->preemph_max(intel_dp);
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drm_WARN_ON_ONCE(&i915->drm,
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preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 &&
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preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3);
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preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy);
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if (p >= preemph_max)
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p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
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v = min(v, dp_voltage_max(p));
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voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);
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drm_WARN_ON_ONCE(&i915->drm,
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voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
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voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);
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voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy);
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if (v >= voltage_max)
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v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
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@ -137,11 +305,21 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
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intel_dp->train_set[lane] = v | p;
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}
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static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,
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enum drm_dp_phy dp_phy)
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{
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return dp_phy == DP_PHY_DPRX ?
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DP_TRAINING_PATTERN_SET :
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DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy);
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}
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static bool
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intel_dp_set_link_train(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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enum drm_dp_phy dp_phy,
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u8 dp_train_pat)
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{
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int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
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u8 buf[sizeof(intel_dp->train_set) + 1];
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int len;
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@ -153,29 +331,33 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
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memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
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len = crtc_state->lane_count + 1;
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return drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
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buf, len) == len;
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return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
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}
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static bool
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intel_dp_reset_link_train(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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enum drm_dp_phy dp_phy,
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u8 dp_train_pat)
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{
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memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
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intel_dp_set_signal_levels(intel_dp, crtc_state);
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return intel_dp_set_link_train(intel_dp, crtc_state, dp_train_pat);
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return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);
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}
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static bool
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intel_dp_update_link_train(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state)
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const struct intel_crtc_state *crtc_state,
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enum drm_dp_phy dp_phy)
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{
|
|
|
|
|
int reg = dp_phy == DP_PHY_DPRX ?
|
|
|
|
|
DP_TRAINING_LANE0_SET :
|
|
|
|
|
DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
intel_dp_set_signal_levels(intel_dp, crtc_state);
|
|
|
|
|
|
|
|
|
|
ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
|
|
|
|
|
ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
|
|
|
|
|
intel_dp->train_set, crtc_state->lane_count);
|
|
|
|
|
|
|
|
|
|
return ret == crtc_state->lane_count;
|
|
|
|
@ -240,10 +422,23 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Perform the link training clock recovery phase using training pattern 1. */
|
|
|
|
|
static void intel_dp_link_training_clock_recovery_delay(struct intel_dp *intel_dp,
|
|
|
|
|
enum drm_dp_phy dp_phy)
|
|
|
|
|
{
|
|
|
|
|
if (dp_phy == DP_PHY_DPRX)
|
|
|
|
|
drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
|
|
|
|
|
else
|
|
|
|
|
drm_dp_lttpr_link_train_clock_recovery_delay();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Perform the link training clock recovery phase on the given DP PHY using
|
|
|
|
|
* training pattern 1.
|
|
|
|
|
*/
|
|
|
|
|
static bool
|
|
|
|
|
intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
|
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
|
enum drm_dp_phy dp_phy)
|
|
|
|
|
{
|
|
|
|
|
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
|
|
|
|
|
u8 voltage;
|
|
|
|
@ -251,7 +446,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
|
|
|
|
|
bool max_vswing_reached = false;
|
|
|
|
|
|
|
|
|
|
/* clock recovery */
|
|
|
|
|
if (!intel_dp_reset_link_train(intel_dp, crtc_state,
|
|
|
|
|
if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,
|
|
|
|
|
DP_TRAINING_PATTERN_1 |
|
|
|
|
|
DP_LINK_SCRAMBLING_DISABLE)) {
|
|
|
|
|
drm_err(&i915->drm, "failed to enable link training\n");
|
|
|
|
@ -275,9 +470,10 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
|
|
|
|
|
for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
|
|
|
|
|
u8 link_status[DP_LINK_STATUS_SIZE];
|
|
|
|
|
|
|
|
|
|
drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
|
|
|
|
|
intel_dp_link_training_clock_recovery_delay(intel_dp, dp_phy);
|
|
|
|
|
|
|
|
|
|
if (!intel_dp_get_link_status(intel_dp, link_status)) {
|
|
|
|
|
if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
|
|
|
|
|
link_status) < 0) {
|
|
|
|
|
drm_err(&i915->drm, "failed to get link status\n");
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
@ -301,8 +497,9 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
|
|
|
|
|
voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
|
|
|
|
|
|
|
|
|
|
/* Update training set as requested by target */
|
|
|
|
|
intel_dp_get_adjust_train(intel_dp, crtc_state, link_status);
|
|
|
|
|
if (!intel_dp_update_link_train(intel_dp, crtc_state)) {
|
|
|
|
|
intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
|
|
|
|
|
link_status);
|
|
|
|
|
if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
|
|
|
|
|
drm_err(&i915->drm,
|
|
|
|
|
"failed to update link training\n");
|
|
|
|
|
return false;
|
|
|
|
@ -329,7 +526,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
|
|
|
|
|
* or 1.2 devices that support it, Training Pattern 2 otherwise.
|
|
|
|
|
*/
|
|
|
|
|
static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
|
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
|
enum drm_dp_phy dp_phy)
|
|
|
|
|
{
|
|
|
|
|
bool source_tps3, sink_tps3, source_tps4, sink_tps4;
|
|
|
|
|
|
|
|
|
@ -338,9 +536,11 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
|
|
|
|
|
* for all downstream devices that support HBR3. There are no known eDP
|
|
|
|
|
* panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
|
|
|
|
|
* specification.
|
|
|
|
|
* LTTPRs must support TPS4.
|
|
|
|
|
*/
|
|
|
|
|
source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
|
|
|
|
|
sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
|
|
|
|
|
sink_tps4 = dp_phy != DP_PHY_DPRX ||
|
|
|
|
|
drm_dp_tps4_supported(intel_dp->dpcd);
|
|
|
|
|
if (source_tps4 && sink_tps4) {
|
|
|
|
|
return DP_TRAINING_PATTERN_4;
|
|
|
|
|
} else if (crtc_state->port_clock == 810000) {
|
|
|
|
@ -357,7 +557,8 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
|
|
|
|
|
* all sinks follow the spec.
|
|
|
|
|
*/
|
|
|
|
|
source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
|
|
|
|
|
sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
|
|
|
|
|
sink_tps3 = dp_phy != DP_PHY_DPRX ||
|
|
|
|
|
drm_dp_tps3_supported(intel_dp->dpcd);
|
|
|
|
|
if (source_tps3 && sink_tps3) {
|
|
|
|
|
return DP_TRAINING_PATTERN_3;
|
|
|
|
|
} else if (crtc_state->port_clock >= 540000) {
|
|
|
|
@ -372,13 +573,28 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
|
|
|
|
|
return DP_TRAINING_PATTERN_2;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
intel_dp_link_training_channel_equalization_delay(struct intel_dp *intel_dp,
|
|
|
|
|
enum drm_dp_phy dp_phy)
|
|
|
|
|
{
|
|
|
|
|
if (dp_phy == DP_PHY_DPRX) {
|
|
|
|
|
drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
|
|
|
|
|
} else {
|
|
|
|
|
const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
|
|
|
|
|
|
|
|
|
|
drm_dp_lttpr_link_train_channel_eq_delay(phy_caps);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Perform the link training channel equalization phase using one of training
|
|
|
|
|
* pattern 2, 3 or 4 depending on the source and sink capabilities.
|
|
|
|
|
* Perform the link training channel equalization phase on the given DP PHY
|
|
|
|
|
* using one of training pattern 2, 3 or 4 depending on the source and
|
|
|
|
|
* sink capabilities.
|
|
|
|
|
*/
|
|
|
|
|
static bool
|
|
|
|
|
intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
|
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
|
enum drm_dp_phy dp_phy)
|
|
|
|
|
{
|
|
|
|
|
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
|
|
|
|
|
int tries;
|
|
|
|
@ -386,22 +602,23 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
|
|
|
|
|
u8 link_status[DP_LINK_STATUS_SIZE];
|
|
|
|
|
bool channel_eq = false;
|
|
|
|
|
|
|
|
|
|
training_pattern = intel_dp_training_pattern(intel_dp, crtc_state);
|
|
|
|
|
training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);
|
|
|
|
|
/* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
|
|
|
|
|
if (training_pattern != DP_TRAINING_PATTERN_4)
|
|
|
|
|
training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
|
|
|
|
|
|
|
|
|
|
/* channel equalization */
|
|
|
|
|
if (!intel_dp_set_link_train(intel_dp, crtc_state,
|
|
|
|
|
if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,
|
|
|
|
|
training_pattern)) {
|
|
|
|
|
drm_err(&i915->drm, "failed to start channel equalization\n");
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (tries = 0; tries < 5; tries++) {
|
|
|
|
|
|
|
|
|
|
drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
|
|
|
|
|
if (!intel_dp_get_link_status(intel_dp, link_status)) {
|
|
|
|
|
intel_dp_link_training_channel_equalization_delay(intel_dp,
|
|
|
|
|
dp_phy);
|
|
|
|
|
if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
|
|
|
|
|
link_status) < 0) {
|
|
|
|
|
drm_err(&i915->drm,
|
|
|
|
|
"failed to get link status\n");
|
|
|
|
|
break;
|
|
|
|
@ -426,8 +643,9 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Update training set as requested by target */
|
|
|
|
|
intel_dp_get_adjust_train(intel_dp, crtc_state, link_status);
|
|
|
|
|
if (!intel_dp_update_link_train(intel_dp, crtc_state)) {
|
|
|
|
|
intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
|
|
|
|
|
link_status);
|
|
|
|
|
if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
|
|
|
|
|
drm_err(&i915->drm,
|
|
|
|
|
"failed to update link training\n");
|
|
|
|
|
break;
|
|
|
|
@ -441,17 +659,16 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
|
|
|
|
|
"Channel equalization failed 5 times\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (intel_dp->set_idle_link_train)
|
|
|
|
|
intel_dp->set_idle_link_train(intel_dp, crtc_state);
|
|
|
|
|
|
|
|
|
|
return channel_eq;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp)
|
|
|
|
|
static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,
|
|
|
|
|
enum drm_dp_phy dp_phy)
|
|
|
|
|
{
|
|
|
|
|
int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
|
|
|
|
|
u8 val = DP_TRAINING_PATTERN_DISABLE;
|
|
|
|
|
|
|
|
|
|
return drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, &val, 1) == 1;
|
|
|
|
|
return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
@ -478,33 +695,34 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp,
|
|
|
|
|
intel_dp_program_link_training_pattern(intel_dp,
|
|
|
|
|
crtc_state,
|
|
|
|
|
DP_TRAINING_PATTERN_DISABLE);
|
|
|
|
|
intel_dp_disable_dpcd_training_pattern(intel_dp);
|
|
|
|
|
intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static bool
|
|
|
|
|
intel_dp_link_train(struct intel_dp *intel_dp,
|
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
|
intel_dp_link_train_phy(struct intel_dp *intel_dp,
|
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
|
enum drm_dp_phy dp_phy)
|
|
|
|
|
{
|
|
|
|
|
struct intel_connector *intel_connector = intel_dp->attached_connector;
|
|
|
|
|
char phy_name[10];
|
|
|
|
|
bool ret = false;
|
|
|
|
|
|
|
|
|
|
intel_dp_prepare_link_train(intel_dp, crtc_state);
|
|
|
|
|
|
|
|
|
|
if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state))
|
|
|
|
|
if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy))
|
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
|
|
if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state))
|
|
|
|
|
if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy))
|
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
|
|
ret = true;
|
|
|
|
|
|
|
|
|
|
out:
|
|
|
|
|
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
|
|
|
|
|
"[CONNECTOR:%d:%s] Link Training %s at link rate = %d, lane count = %d",
|
|
|
|
|
"[CONNECTOR:%d:%s] Link Training %s at link rate = %d, lane count = %d, at %s",
|
|
|
|
|
intel_connector->base.base.id,
|
|
|
|
|
intel_connector->base.name,
|
|
|
|
|
ret ? "passed" : "failed",
|
|
|
|
|
crtc_state->port_clock, crtc_state->lane_count);
|
|
|
|
|
crtc_state->port_clock, crtc_state->lane_count,
|
|
|
|
|
intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
@ -528,6 +746,36 @@ static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
|
|
|
|
|
schedule_work(&intel_connector->modeset_retry_work);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Perform the link training on all LTTPRs and the DPRX on a link. */
|
|
|
|
|
static bool
|
|
|
|
|
intel_dp_link_train_all_phys(struct intel_dp *intel_dp,
|
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
|
int lttpr_count)
|
|
|
|
|
{
|
|
|
|
|
bool ret = true;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
intel_dp_prepare_link_train(intel_dp, crtc_state);
|
|
|
|
|
|
|
|
|
|
for (i = lttpr_count - 1; i >= 0; i--) {
|
|
|
|
|
enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i);
|
|
|
|
|
|
|
|
|
|
ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy);
|
|
|
|
|
intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy);
|
|
|
|
|
|
|
|
|
|
if (!ret)
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
|
intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
|
|
|
|
|
|
|
|
|
|
if (intel_dp->set_idle_link_train)
|
|
|
|
|
intel_dp->set_idle_link_train(intel_dp, crtc_state);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* intel_dp_start_link_train - start link training
|
|
|
|
|
* @intel_dp: DP struct
|
|
|
|
@ -545,8 +793,8 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
|
|
|
|
|
* TODO: Reiniting LTTPRs here won't be needed once proper connector
|
|
|
|
|
* HW state readout is added.
|
|
|
|
|
*/
|
|
|
|
|
intel_dp_lttpr_init(intel_dp);
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int lttpr_count = intel_dp_lttpr_init(intel_dp);
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if (!intel_dp_link_train(intel_dp, crtc_state))
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if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count))
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intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
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}
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